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PDF 25LC1024 Data sheet ( Hoja de datos )
| Número de pieza | 25LC1024 | |
| Descripción | 1 Mbit SPI Bus Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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25AA1024/25LC1024
1 Mbit SPI Bus Serial EEPROM
Device Selection Table
Part Number
25LC1024
25AA1024
VCC Range
2.5-5.5V
1.8-5.5V
Page Size
256 Byte
256 Byte
Features:
• 20 MHz max. Clock Speed
• Byte and Page-level Write Operations:
- 256 byte page
- 6 ms max. write cycle time
- No page or sector erase required
• Low-Power CMOS Technology:
- Max. Write current: 5 mA at 5.5V, 20 MHz
- Read current: 7 mA at 5.5V, 20 MHz
- Standby current: 1μA at 2.5V
(Deep power-down)
• Electronic Signature for Device ID
• Self-Timed Erase and Write Cycles:
- Page Erase (6 ms max.)
- Sector Erase (10 ms max.)
- Chip Erase (10 ms max.)
• Sector Write Protection (32K byte/sector):
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1M erase/write cycles
• Temperature Ranges Supported:
- Industrial (I):
- Automotive (E):
-40°C to +85°C
-40°C to +125°C
• Pb-free packages available
Pin Function Table
Name
Function
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
Chip Select Input
Serial Data Output
Write-Protect
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Temp. Ranges
I,E
I
Packages
P, SM, MF
P, SM, MF
Description:
The Microchip Technology Inc. 25AA1024/25LC1024
(25XX1024*) is a 1024 Kbit serial EEPROM memory
with byte-level and page-level serial EEPROM func-
tions. It also features Page, Sector and Chip erase
functions typically associated with Flash-based prod-
ucts. These functions are not required for byte or page
write operations. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled by a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX1024 is available in standard packages
including 8-lead PDIP and SOIJ, and advanced 8-lead
DFN package. All devices are Pb-free.
Package Types (not to scale)
CS 1
SO 2
WP 3
VSS 4
DFN
(MF)
8 VCC
7 HOLD
6 SCK
5 SI
PDIP/SOIJ
(P, SM)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
*25XX1024 is used in this document as a generic part number
for the 25AA1024, 25LC1024 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS21836D-page 1
1 page  
25AA1024/25LC1024
FIGURE 1-1: HOLD TIMING
CS
16
SCK
SO n + 2
n+1
17
18
n
16 17
19
High-Impedance
n
SI
n+2
n+1
n
Don’t Care
5
n
HOLD
n-1
n-1
FIGURE 1-2: SERIAL INPUT TIMING
CS
2
Mode 1,1
SCK Mode 0,0
5
6
SI MSB in
SO
7
High-Impedance
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
9 10
13
MSB out
Don’t Care
8
14
4
12
11
3
LSB in
3
Mode 1,1
Mode 0,0
15
LSB out
© 2007 Microchip Technology Inc.
Preliminary
DS21836D-page 5
5 Page 
25AA1024/25LC1024
2.4 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2: STATUS REGISTER
7 654 3 2 1
W/R – – – W/R W/R R
WPEN X X X BP1 BP0 WEL
W/R = writable/readable. R = read-only.
0
R
WIP
The Write-In-Process (WIP) bit indicates whether the
25XX1024 is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
0 00 00 1 01
High-Impedance
Data from STATUS register
7 6 54 3 2 10
© 2007 Microchip Technology Inc.
Preliminary
DS21836D-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet 25LC1024.PDF ] | |
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