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PDF 25C160 Data sheet ( Hoja de datos )
| Número de pieza | 25C160 | |
| Descripción | 16K SPI Bus Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 25C160 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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Not recommended for new designs –
Please use 25AA160A/B or 25LC160A/B.
25AA160/25LC160/25C160
16K SPI Bus Serial EEPROM
Device Selection Table
Part
Number
25AA160
25LC160
25C160
VCC
Range
1.8-5.5V
2.5-5.5V
4.5-5.5V
Max Clock
Frequency
1 MHz
2 MHz
3 MHz
Temp
Ranges
I
I
I,E
Features:
• Low-power CMOS technology:
- Write current: 3 mA maximum
- Read current: 500 A typical
- Standby current: 500 nA typical
• 2048 x 8-bit organization
• 16 byte page
• Write cycle time: 5 ms max.
• Self-timed erase and write cycles
• Block write protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection:
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability:
- Endurance: 1 M cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP and SOIC packages
• Temperature ranges supported:
- Industrial (I):
-40C to +85C
- Automotive (E) (25C160): -40°C to +125°C
Description:
The Microchip Technology Inc. 25AA160/25LC160/
25C160 (25XX160*) are 16 Kbit Serial Electrically
Erasable PROMs. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.
Package Types
PDIP/SOIC
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
Block Diagram
Status
Register
HV Generator
I/O Control
Logic
Memory
Control
Logic
X
Dec
EEPROM
Array
Page Latches
SI
SO
CS
SCK
HOLD
WP
VCC
VSS
Y Decoder
Sense Amp.
R/W Control
1997-2012 Microchip Technology Inc.
DS21231E-page 1
1 page  
25AA160/25LC160/25C160
1.3 AC Test Conditions
AC Waveform:
VLO = 0.2V
—
VHI = VCC - 0.2V
(Note 1)
VHI = 4.0V
(Note 2)
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC 4.0V
2: For VCC > 4.0V
FIGURE 1-4:
AC TEST CIRCUIT
VCC
2.25 K
SO
1.8 K
100 pF
1997-2012 Microchip Technology Inc.
DS21231E-page 5
5 Page 
25AA160/25LC160/25C160
FIGURE 3-7:
WRITE STATUS REGISTER TIMING SEQUENCE
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
instruction
data to Status register
0 00 00 0 01 7 6 54 3 2 10
High-impedance
SO
3.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A WRITE ENABLE instruction must be issued to
set the write enable latch
• After a byte write, page write, or Status register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
3.8 Power On State
The 25XX160 powers on in the following state:
• The device is in low power Standby mode (CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A low level on CS is required to enter active state
TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN
X
0
1
X
WP
X
X
Low
High
WEL
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Writable
Writable
Status Register
Protected
Writable
Protected
Writable
1997-2012 Microchip Technology Inc.
DS21231E-page 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 25C160.PDF ] | |
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