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PDF RF5184 Data sheet ( Hoja de datos )

Número de pieza RF5184
Descripción W-CDMA POWER AMPLIFIER MODULE
Fabricantes RF Micro Devices 
Logotipo RF Micro Devices Logotipo



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Typical Applications
• 3V W-CDMA Cellular Handset (Band 5)
RF5184
DUAL-BAND 800MHz/1900MHz
W-CDMA POWER AMPLIFIER MODULE
• 3V W-CDMA US-PCS Handset (Band 2)
Product Description
The RF5184 is a high-power, high-efficiency linear ampli-
fier module specifically designed for 3V handheld sys-
tems. The device is manufactured on an advanced third
generation GaAs HBT process, and was designed for use
as the final RF amplifier in W-CDMA handheld digital cel-
lular equipment, spread-spectrum systems, and other
applications in the 824MHz to 849MHz band (Band 5)
and 1850MHz to 1910MHz band (Band 2). The RF5184
has a digital control line for low power applications to
lower quiescent current. The RF5184 is assembled in a
24-pin, 4mmx4mm, QFN package.
Optimum Technology Matching® Applied
Si BJT
9GaAs HBT
GaAs MESFET
Si Bi-CMOS
SiGe HBT
Si CMOS
InGaP/HBT
GaN HEMT
SiGe Bi-CMOS
24 23 22 21 20 19
VREG - PCS 1
RF IN - PCS 2
Bias
PCS
18 NC
17 NC
VREG - CELL 3
VMODE - CELL 4
Bias
Cell
16 RF OUT - PCS
15 NC
RF IN - CELL 5
14 RF OUT - CELL
VCC1 - CELL 6
13 NC
7 8 9 10 11 12
Functional Block Diagram
0.10 C
4.0
-A-
-B-
1.00
0.80
4.0
0.10 C B
2 PL
0.10 C A
2 PL
0.50 TYP
0.10 C A B
2.60
2.40
2
PL
0.2 C
Shaded area indicates pin 1.
Dimensions in mm.
-C-
0.55
0.35TYP
SEATING
PLANE
Scale: None
0.10 C
0.203
TYP
0.08 C
0.05
0.00
TYP
0.30
0.18
TYP
0.10 M C A B
TYP00..0083
0.50TYP
0.30
Package Style: QFN, 24-Pin, 4x4
Features
• Input/Output Internally Matched@50Ω
• 43% Peak Linear Efficiency for Cell Band
• -41dBc ACLR @ 5MHz for Cell Band
• -40dBc ACLR@5MHz for PCS Band
• 44% Peak Linear Efficiency for PCS Band
• HSDPA Capable
Ordering Information
RF5184
Dual-Band 800MHz/1900MHz W-CDMA Power
Amplifier Module
RF5184PCBA-410 Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev A0 060323
2-689

1 page




RF5184 pdf
RF5184
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pkg
Base
Function Description
VREG_PCS
RFIN_PCS
Regulated voltage supply for PCS band amplifier bias circuit. In power
down mode, both VREG_PCS and VMODE_PCS need to be LOW (<0.5V).
PCS band RF input internally matched to 50Ω. This input is internally
AC-coupled.
VREG_Cell
VMODE_
Cell
Regulated voltage supply for Cell band amplifier bias circuit. In power
down mode, both VREG_Cell and VMODE_Cell need to be LOW (<0.5V).
Cell band mode control pin. For nominal operation (High Power mode),
VMODE_Cell is set LOW. When set HIGH, devices are biased lower to
improve efficiency.
RFIN_Cell Cell band RF input internally matched to 50Ω. This input is internally
AC-coupled.
VCC1_Cell Cell band first stage collector supply. A 2200uF and a 4.7μF decou-
pling capacitors are required.
NC No connection. Do not connect this pin to any external circuit.
NC No connection. Do not connect this pin to any external circuit.
VCC2_Cell Cell band output stage collector supply. Please see the schematic for
required external components.
VCC2_Cell Same as Pin 9.
VCC2_Cell Same as Pin 9.
NC No connection. Do not connect this pin to any external circuit.
NC No connection. Do not connect this pin to any external circuit.
RFOUT_Cell Cell band RF output. Internally AC-coupled.
NC No connection. Do not connect this pin to any external circuit.
RFOUT_ PCS band RF output. Internally AC-coupled.
PCS
NC No connection. Do not connect this pin to any external circuit.
NC No connection. Do not connect this pin to any external circuit.
VCC2_PCS PCS band output stage collector supply. Please see the schematic for
required external components.
VCC2_PCS Same as Pin 19.
VCC2_PCS Same as Pin 19.
VCC1_PCS PCS band first stage collector supply. A 4.7μF decoupling capacitor is
required.
VCC BIAS Bias circuit supply voltage.
VMODE_
PCS
PCS band mode control pin. For nominal operation (High Power mode),
VMODE_PCS is set Low. When set HIGH, devices are biased lower to
improve efficiency.
GND
The backside of the package should be soldered to a top side ground
pad which is connected to the ground plane with multiple vias. The pad
should have a short thermal path to the ground plane.
Interface Schematic
Rev A0 060323
2-693

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