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PDF KSZ8041NL Data sheet ( Hoja de datos )
| Número de pieza | KSZ8041NL | |
| Descripción | 10Base-T/100Base-TX Physical Layer Transceiver | |
| Fabricantes | Micrel Semiconductor | |
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KSZ8041NL
10Base-T/100Base-TX
Physical Layer Transceiver
General Description
The KSZ8041NL is a single supply 10Base-T/100Base-TX
Physical Layer Transceiver, which provides MII/RMII
interfaces to transmit and receive data. An unique mixed
signal design extends signaling distance while reducing
power consumption.
HP Auto MDI/MDI-X provides the most robust solution for
eliminating the need to differentiate between crossover
and straight-through cables.
The KSZ8041NL represents a new level of features and
performance and is an ideal choice of physical layer
transceiver for 10Base-T/100Base-TX applications.
The KSZ8041NL comes in a 32-pin, lead-free MLF® (QFN
per JDEC) package (See Ordering Information).
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2006
M9999-102406-1.0
1 page  
Micrel, Inc.
KSZ8041NL
Reference Circuit for Power and Ground Connections .................................................................................................... 23
Register Map........................................................................................................................................................................ 24
Register Description ........................................................................................................................................................... 24
Absolute Maximum Ratings(1) ............................................................................................................................................ 31
Operating Ratings(2) ............................................................................................................................................................ 31
Electrical Characteristics(4) ................................................................................................................................................ 31
Timing Diagrams ................................................................................................................................................................. 33
MII SQE Timing (10Base-T) ............................................................................................................................................. 33
MII Transmit Timing (10Base-T) ....................................................................................................................................... 34
MII Receive Timing (10Base-T) ........................................................................................................................................ 35
MII Transmit Timing (100Base-TX)................................................................................................................................... 36
MII Receive Timing (100Base-TX).................................................................................................................................... 37
RMII Timing....................................................................................................................................................................... 38
Auto-Negotiation Timing ................................................................................................................................................... 39
MDC/MDIO Timing............................................................................................................................................................ 40
Reset Timing..................................................................................................................................................................... 41
Reset Circuit ........................................................................................................................................................................ 42
Reference Circuits for LED Strapping Pins...................................................................................................................... 43
Selection of Isolation Transformer.................................................................................................................................... 44
Selection of Reference Crystal .......................................................................................................................................... 44
Package Information........................................................................................................................................................... 45
October 2006
5 M9999-102406-1.0
5 Page 
Micrel, Inc.
KSZ8041NL
31
LED1 /
Ipu/O
LED Output: Programmable LED1 Output /
SPEED
Config Mode:
Latched as SPEED (register 0h, bit 13) during power-up / reset.
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Speed
Pin State
10BT
H
100BT
L
LED Definition
OFF
ON
LED mode = [01]
Activity
Pin State
No Activity
H
Activity
L
LED Definition
OFF
ON
LED mode = [10]
Reserved
LED mode = [11]
Reserved
32
RST#
I
Chip Reset (active low)
PADDLE
GND
Gnd Ground
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down.
Ipu = Input with internal pull-up.
Opu = Output with internal pull-up.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII.
RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered
data are sent from the PHY.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
received by the PHY from the MAC.
October 2006
11 M9999-102406-1.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8041NL.PDF ] | |
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