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PDF XRT72L71 Data sheet ( Hoja de datos )
| Número de pieza | XRT72L71 | |
| Descripción | DS3 ATM UNI/CLEAR CHANNEL FRAMER | |
| Fabricantes | Exar Corporation | |
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XRT72L71
AUGUST 2002
GENERAL DESCRIPTION
The XRT72L71 DS3 ATM User Network Interface
(UNI)/Clear-Channel Framer is designed to function
as either a DS3 ATM UNI or Clear channel framer.
For ATM UNI applications, this device provides the
ATM Physical Layer (Physical Medium Dependent
and Transmission Convergence sub-layers) interface
for both the public and private networks at DS3 rates.
For Clear-Channel framer applications, this device
supports the transmission and reception of “user da-
ta” via the DS3 payload bits.
The XRT72L71incorporates Receive, Transmit, Micro-
processor Interface, Performance Monitor, Test and Di-
agnostic and Line Interface Unit Scan Drive sections.
APPLICATIONS
• Private User Network Interfaces
• ATM Switches
• ATM Concentrators
• DSLAM Equipment
• DS3 Frame Relay Equipment
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
FEATURES
• Compliant with UTOPIA Level 1 and 2 with 8 or 16
Bit Interface Specification and supports UTOPIA
Bus speeds of up to 50 MHz
• Contains on-chip 16 cell FIFO in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit OAM Cell buffer
and a 108 byte Receive OAM cell buffer, for trans-
mission, reception and processing of OAM cells.
• Supports PLCP or ATM Direct Mapping modes
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3 Clear Channel Framing Applications
• Includes PRBS Generator and Receiver
• Supports Local, Remote-Line, Cell, and PLCP
Loop-backs
• Interfaces to 8 or 16 Bit wide Motorola and Intel µPs
• Low power 3.3V, 5V input tolerant, CMOS
• 160 pin PQFP Package
• 3 and 4 Channel Version also Available
FIGURE 1. XRT72L71 SIMPLIFIED BLOCK DIAGRAM WITH SYSTEM INTERFACES
UTOPIA BUS
Level 1 or 2
ATM
Layer
Processor
TxUClav
16
Address 5
XRT72L71
Tx
UTOPIA
Interface
Tx
Cell
Processor
Tx
PLCP
Processor
Performance
Monitor
FEAC
Processor
LAPD
Transceiver
Microprocessor
Interface
Tx
DS3
Framer
LIU
Interface
Drive
and
Scan
Address 5
16
RxUClav
Rx
UTOPIA
Interface
Rx
Cell
Processor
Rx
PLCP
Processor
Rx
DS3
Framer
ATM Switch
25, 33 or 50 MHz
D[15:0]
D[7:0]
A[8:0]
WR_RW
4 ALE_AS
RD_DS
RDY_DTCK
Intel/Motorola µP
Configuration, Control and Status Monitor
TxPOS
TxNEG
TCK
DMO
RLOS
RLOL
XRT73L00
TPDATA
TNDATA Tx
TCK
DMO
RLOS
RLOL
LLOOP
RLOOP
TAOS
TxLEV
EncoDis
Req
LLB
RLB
TAOS
TxLEV
ENCODIS
ReQDIS
RxPOS
RxNEG
RxLineClk
RPOS
RNEG
RCLK1
Rx
DS3/E3 LIU
75Ω coax
DS3
44.736 MHz
75Ω coax
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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DS3 ATM UNI/CLEAR CHANNEL FRAMER IC XRT72L71
REV. 1.1.0
CLEAR CHANNEL MODE OPERATION ........................................................................................................... 40
Features ......................................................................................................................... 41
Transmit and Receive Sections ................................................................................... 41
UTOPIA Interface Blocks ...................................................................................................................... 41
Transmit Cell Processor Block .............................................................................................................. 42
Receive Cell Processor Block ............................................................................................................... 42
Transmit PLCP Processor Block ........................................................................................................... 42
Receive PLCP Processor Block ............................................................................................................ 42
Transmit/Receive DS3 Framer Block .................................................................................................... 42
Microprocessor Interface Section .......................................................................................................... 42
Performance Monitor Section ................................................................................................................ 43
Test and Diagnostic Section ................................................................................................................. 43
Line Interface Drive and Scan Section .................................................................................................. 43
LIST OF REGISTERS ....................................................................................................... 44
REGISTER SUMMARY LIST .......................................................................................................................... 44
TABLE 1: UNI OPERATING MODE REGISTER ...................................................................................................... 46
TABLE 2: UNI I/O CONTROL REGISTER ............................................................................................................. 47
TABLE 3: PART NUMBER REGISTER ................................................................................................................... 47
TABLE 4: VERSION NUMBER REGISTER ............................................................................................................. 47
TABLE 5: UNI INTERRUPT ENABLE REGISTER .................................................................................................... 48
TABLE 6: UNI INTERRUPT STATUS REGISTER .................................................................................................... 49
TABLE 7: TEST CELL CONTROL AND STATUS REGISTER ..................................................................................... 50
TABLE 8: TEST CELL ERROR ACCUMULATOR HOLDING REGISTER ...................................................................... 51
TABLE 9: TEST CELL HEADER BYTE-1 ............................................................................................................... 51
TABLE 10: TEST CELL HEADER BYTE-2 ............................................................................................................. 51
TABLE 11: TEST CELL HEADER BYTE-3 ............................................................................................................. 51
TABLE 12: TEST CELL HEADER BYTE-4 ............................................................................................................. 51
TABLE 13: TEST CELL ERROR ACCUMULATOR - MSB ........................................................................................ 52
TABLE 14: TEST CELL ERROR ACCUMULATOR - LSB ......................................................................................... 52
TABLE 15: RX DS3 CONFIGURATION AND STATUS REGISTER ............................................................................. 53
TABLE 16: RXDS3 STATUS REGISTER .............................................................................................................. 54
TABLE 17: RX DS3 INTERRUPT ENABLE REGISTER ............................................................................................ 54
TABLE 18: RX DS3 INTERRUPT STATUS REGISTER ............................................................................................ 55
TABLE 19: RX DS3 FEAC REGISTER ................................................................................................................ 55
TABLE 20: RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER .................................................................... 56
TABLE 21: RX DS3 LAPD CONTROL REGISTER ................................................................................................ 57
TABLE 22: RX DS3 LAPD STATUS REGISTER ................................................................................................... 58
TABLE 23: TX DS3 CONFIGURATION REGISTER ................................................................................................. 59
TABLE 24: TX DS3 M-BIT MASK REGISTER ....................................................................................................... 60
TABLE 25: TX DS3 F-BIT MASK1 REGISTER ...................................................................................................... 60
TABLE 26: TX DS3 F-BIT MASK2 REGISTER ...................................................................................................... 61
TABLE 27: TX DS3 F-BIT MASK3 REGISTER ...................................................................................................... 61
TABLE 28: TX DS3 F-BIT MASK4 REGISTER ...................................................................................................... 61
TABLE 29: TX DS3 FEAC CONFIGURATION AND STATUS REGISTER ................................................................... 62
TABLE 30: TX DS3 FEAC REGISTER ................................................................................................................ 62
TABLE 31: TX DS3 LAPD CONFIGURATION REGISTER ....................................................................................... 63
TABLE 32: TX DS3 LAPD STATUS/INTERRUPT REGISTER .................................................................................. 64
TABLE 33: PMON LCV EVENT COUNT REGISTER - MSB .................................................................................. 64
TABLE 34: PMON LCV EVENT COUNT REGISTER - LSB ................................................................................... 64
TABLE 35: PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB .......................................................... 65
TABLE 36: PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB ........................................................... 65
TABLE 37: PMON P-BIT ERROR COUNT REGISTER - MSB ................................................................................ 65
TABLE 38: PMON P-BIT ERROR COUNT REGISTER - LSB ................................................................................. 65
TABLE 39: PMON FEBE EVENT COUNT REGISTER - MSB ................................................................................ 65
II
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PIN DESCRIPTION (CONTINUED)
PIN NO.
24
SYMBOL
TxLev
TYPE
O
25 D1 I/O
26 RLOOP
O
27 D0 I/O
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
DESCRIPTION
Transmit Line Build Enable/Disable Select (to be connected to the TxLev
input pin of the XRT7300 E3/DS3/STS-1 LIU IC): This output pin is intended
to be connected to the TxLev input pin of the XRT7300 E3/DS3/STS-1 LIU IC.
The user can control the state of this output pin by writing a “0” or a “1” to Bit 2
(TxLev) within the Line Interface Driver Register (Address = 0x72).
If the user commands this signal to toggle “High” then it will disable the “Trans-
mit Line Build-Out” circuitry within the XRT7300. In this case, the XRT7300
will output unshaped (square-wave) pulses onto the “Transmit Line Signal”. In
order to insure that the XRT7300 generates a line signal that is compliant with
the Bellcore GR-499-CORE Pulse Template requirements (at the DSX-3
Cross-Connect), the user is advised to set this output pin “High”, if the cable
length (between the Transmit Output of the XRT7300 and the DSX-3 Cross-
Connect) is greater than 225 feet.
Conversely, if the user commands this signal to toggle “High”, then it will
enable the “Transmit Line Build-Out” circuitry within the XRT7300. In this case,
the XRT7300 will output shaped pulses onto the “Transmit Line Signal”. In
order to ensure that the XRT7300 generates a line signal that is compliant
with the Bellcore GR-499-CORE Pulse Template requirements (at the DSX-3
Cross-Connect), the user is advised to set this output pin “Low”, if the cable
length (between the Transmit Output of the XRT7300 and the DSX-3 Cross
Connect) is less than 225 ft. of cable.
Writing a “1” to Bit 2 of the Line Interface Drive Register (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause
this output pin to toggle “Low”.
NOTE: If the customer is not using the XRT7300 DS3/E3/STS-1 LIU IC, then
this output pin can be used for other purposes.
Bi-Directional Data bus (Microprocessor Interface Section):
Please see description for D15, pin1.
Remote Loop-back Output Pin (to the XRT7300 DS3/E3/STS-1 LIU IC):
This output pin is intended to be connected to the RLOOP input pin of the
XRT7300 LIU IC. This output pin, along with the LLOOP input pin (pin 28) per-
mits the user to configure the XRT7300 to operate in either of the following three
(3) loop-back modes.
• Analog Local Loop-back Mode
• Digital Local Loop-back Mode
• Remote Loop-back Mode.
Writing a “1” to bit 1 of the “Line Interface Drive Register (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause
the RLOOP output to toggle “Low”.
NOTE: If the customer is not using the XRT7300 DS3/E3/STS-1 IC, then this
output pin can be used for other purposes.
Bi-Directional Data bus (Microprocessor Interface Section):
Please see description for D15, pin1.
7
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