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PDF XRT72L52 Data sheet ( Hoja de datos )
| Número de pieza | XRT72L52 | |
| Descripción | TWO CHANNEL DS3/E3 FRAMER IC | |
| Fabricantes | Exar | |
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PRELIMINARY
XRT72L52
JANUARY 2001
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
GENERAL DESCRIPTION
The XRT72L52, 2 Channel DS3/E3 Framer IC is de-
signed to accept “User Data” from the Terminal
Equipment and insert this data into the “payload” bit-
fields within an “outbound” DS3/E3 Data Stream. Fur-
ther, the Framer IC is also designed to receive an “in-
bound” DS3/E3 Data Stream (from the Remote Ter-
minal Equipment) and extract out the “User Data”.
The XRT72L52 DS3/E3 Framer device is designed to
support full-duplex data flow between Terminal Equip-
ment and an LIU (Line Interface Unit) IC. The Framer
Device will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 Framing Formats.
The XRT72L52 DS3/E3 Framer IC consists of two
Transmit sections, two Receiver sections, two Perfor-
mance Monitor Sections and a Microprocessor inter-
face.
The Transmit Sections, include a Transmit Payload
Data Input Interface, a Transmit Overhead data Input
Interface Section, a Transmit HDLC Controller, a
Transmit DS3/E3 Framer block and a Transmit LIU In-
terface Block which permits the Terminal Equipment
to transmit data to a remote terminal.
The Receive Sections, consist of a Receive LIU Inter-
face, a Receive DS3/E3 Framer, a Receive HDLC
Controller, a Receive Payload Data Output Interface,
and a Receive Overhead Data Interface which allows
the local terminal equipment to receive data from re-
mote terminal equipment.
The Microprocessor Interface is used to configure the
Framer IC in different operating modes and monitor
the performance of the Framer.
The Performance Monitor Sections consist of a large
number of "Reset-upon-Read" and "Read-Only" reg-
isters that contain cumulative and "one-second" sta-
tistics that reflect the performance/health of the two
channels of the Framer IC/system.
FEATURES
• Transmits, Receives and Processes data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.
• 2 Channel HDLC Controller - Tx and Rx
• Interfaces to all Popular Microprocessors
• Integrated Framer Performance Monitor
• Available in a 160 Pin PQFP package
• 3.3V Power Supply with 5V Tolerant I/O
• Operating Temperature -40°C to +85°C
APPLICATIONS
• Network Interface Units
• CSU/DSU Equipment.
• PCM Test Equipment
• Fiber Optic Terminals
• DS3/E3 Frame Relay Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT72L52
Reset
TestMode
NibbleLnTF
TxOHEnable
TxOHClk
TxOHFrame
TxAISEn
TxOH
TxOHIns
T3/E3
Transmit
Overhead
Interface
TxLineClk[n:0]
TxPOS[n:0]
TxNEG[n:0]
RxLineClk[n:0]
RxPOS[n:0]
RxNEG[n:0]
ExtLOS
RxOHEnable[n:0]
RxOHClk[n:0]
RxOH[n:0]
RxRed[n:0]
RxOHFrame[n:0]
RxOOF[n:0]
LIU
Interface/
Controller
T3/E3
Receive
Overhead
Interface
Typical Channel n
Where n = 0 or 1
T3/E3 Transmit
Framer
T3/E3
transmit
Input
T3 FEAC & Data
Link Controller
Performance
Monitor
Interrupt
Controller
T3/E3 Receive
Framer
T3/E3
Receive
Output
HDLC
controller
uP
Interface
HDLC
controller
TxOHInd[n:0]
TxNibFrame[n:0]
TxFrame[n:0]
TxNibClk[n:0]
TxLnClk[n:0]
TxFrameRef[n:0]
TxNib[n:0]
TxSer[n:0]
A(11:0)
D(7:0)
ALE_AS
WR_R/W
CS
RDY_DTCK
Reset
INT
MOTO
RD_DS
RxClk[n:0]
RxOHind[n:0]
RxFrame[n:0]
RxNib[n:0]
RxSer[n:0]
RxOUTClk[n:0]
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................. 82
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 82
RXE3 NR BYTE REGISTER (ADDRESS = 0X1A) ........................................................................................ 83
RXE3 GC BYTE REGISTER (ADDRESS = 0X1B) ....................................................................................... 83
RXE3 TTB-0 REGISTER (ADDRESS = 0X1C) ............................................................................................ 84
RXE3 TTB-1 REGISTER (ADDRESS = 0X1D) ............................................................................................ 84
RXE3 TTB-2 REGISTER (ADDRESS = 0X1E) ............................................................................................ 84
RXE3 TTB-3 REGISTER (ADDRESS = 0X1F) ............................................................................................ 85
RXE3 TTB-4 REGISTER (ADDRESS = 0X20) ............................................................................................ 85
RXE3 TTB-5 REGISTER (ADDRESS = 0X21) ............................................................................................ 85
RXE3 TTB-6 REGISTER (ADDRESS = 0X22) ............................................................................................ 85
RXE3 TTB-7 REGISTER (ADDRESS = 0X23) ............................................................................................ 86
RXE3 TTB-8 REGISTER (ADDRESS = 0X24) ............................................................................................ 86
RXE3 TTB-9 REGISTER (ADDRESS = 0X25) ............................................................................................ 86
RXE3 TTB-10 REGISTER (ADDRESS = 0X26) .......................................................................................... 87
RXE3 TTB-11 REGISTER (ADDRESS = 0X27) .......................................................................................... 87
RXE3 TTB-12 REGISTER (ADDRESS = 0X28) .......................................................................................... 87
RXE3 TTB-13 REGISTER (ADDRESS = 0X29 ........................................................................................... 87
RXE3 TTB-14 REGISTER (ADDRESS = 0X2A) .......................................................................................... 88
RXE3 TTB-15 REGISTER (ADDRESS = 0X2B) .......................................................................................... 88
RXE3 SSM REGISTER (ADDRESS = 0X2B) ................................................................................................ 88
2.4.4 Receive E3 Framer Configuration Registers (ITU-T G.751) ................................................................... 89
RXE3 CONFIGURATION & STATUS REGISTER - 1 G.751 (ADDRESS = 0X10) ............................................. 89
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ........................................................ 89
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................... 90
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ................................................................... 91
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................... 91
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................... 92
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................. 93
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 93
RXE3 SERVICE BIT REGISTER (ADDRESS = 0X1A) ................................................................................... 94
2.4.5 Transmit DS3 Configuration Registers .................................................................................................... 94
TRANSMIT DS3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................... 95
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) .................................... 96
TXDS3 FEAC REGISTER (ADDRESS = 0X32) .......................................................................................... 97
TXDS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................................. 97
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ..................................................... 98
TXDS3 M-BIT MASK REGISTER (ADDRESS = 0X35) ................................................................................. 98
TXDS3 F-BIT MASK REGISTER - 1 (ADDRESS = 0X36) ............................................................................. 99
TXDS3 F-BIT MASK REGISTER - 2 (ADDRESS = 0X37) ........................................................................... 100
TXDS3 F-BIT MASK REGISTER - 3 (ADDRESS = 0X38) ........................................................................... 100
TXDS3 F-BIT MASK REGISTER - 4 (ADDRESS = 0X39) ........................................................................... 100
2.4.6 Transmit E3 (ITU-T G.832) Configuration Registers ............................................................................. 100
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 101
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................................. 102
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 102
TXE3 GC BYTE REGISTER (ADDRESS = 0X35) ...................................................................................... 103
TXE3 MA BYTE REGISTER (ADDRESS = 0X36) ...................................................................................... 104
TXE3 MA BYTE REGISTER (ADDRESS = 0X36) ...................................................................................... 104
TXE3 NR BYTE REGISTER (ADDRESS = 0X37) ...................................................................................... 104
TXE3 TTB-0 REGISTER (ADDRESS = 0X38) ........................................................................................... 105
TXE3 TTB-1 REGISTER (ADDRESS = 0X39) ........................................................................................... 105
TXE3 TTB-2 REGISTER (ADDRESS = 0X3A) .......................................................................................... 105
TXE3 TTB-3 REGISTER (ADDRESS = 0X3B) .......................................................................................... 106
TXE3 TTB-4 REGISTER (ADDRESS = 0X3C) .......................................................................................... 106
III
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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................ 215
RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19) .......................................................................... 215
TABLE 41: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND
SIZE ...................................................................................................................................................... 216
Figure 86. Flow Chart depicting the Functionality of the LAPD Receiver .......................................... 217
4.3.4 The Receive Overhead Data Output Interface ...................................................................................... 217
Figure 87. A Simple Illustration of the Receive Overhead Output Interface block ............................. 218
TABLE 42: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK ................................................................................................................................ 219
Figure 88. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 1). ............................................................................................................ 219
TABLE 43: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXO-
HFRAME WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT
PIN ....................................................................................................................................................... 220
Figure 89. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method
1). ........................................................................................................................................................ 222
TABLE 44: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (METHOD 2) ............................................................................................................. 223
Figure 90. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 2). ............................................................................................................ 224
TABLE 45: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME
WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN
225
Figure 91. Illustration of the signals that are output via the Receive Overhead Data Output Interface block
(for Method 2). ..................................................................................................................................... 227
4.3.5 The Receive Payload Data Output Interface ......................................................................................... 227
Figure 92. A Simple illustration of the Receive Payload Data Output Interface block ........................ 228
TABLE 46: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
TERFACE BLOCK .................................................................................................................................... 229
Figure 93. Illustration of the XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Terminal Equip-
ment (Serial Mode Operation) ............................................................................................................. 230
Figure 94. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface
block of the XRT72L52 and the Terminal Equipment (Serial Mode Operation) .................................. 231
Figure 95. Illustration of the XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Section of the
Terminal Equipment (Nibble-Mode Operation) ................................................................................... 232
Figure 96. An Illustration of the Behavior of the signals between the Receive Payload Data Output Interface
Block of the XRT72L52 and the Terminal Equipment (Nibble-Mode Operation). ............................... 233
4.3.6 Receive Section Interrupt Processing ................................................................................................... 233
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 234
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 234
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 235
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 235
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 236
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 236
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 236
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 237
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 237
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 238
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 238
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 239
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 239
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 239
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 240
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ...................................................................................... 240
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 240
IX
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