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Número de pieza XRT72L50
Descripción SINGLE CHANNEL DS3/E3 FRAMER IC
Fabricantes Exar Corporation　
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XRT72L50
OCTOBER 2003
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
GENERAL DESCRIPTION
The XRT72L50, single Channel DS3/E3 Framer IC is
designed to accept user data from the Terminal
Equipment and insert this data into the payload bit-
fields within an outbound DS3/E3 Data Stream. Fur-
ther, the Framer IC is also designed to receive an in-
bound DS3/E3 Data Stream from the Remote Termi-
nal Equipment and extract out the user data.
The XRT72L50 DS3/E3 Framer device is designed to
support full-duplex data flow between Terminal Equip-
ment and an LIU (Line Interface Unit) IC. The Framer
Device will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 Framing Formats.
The XRT72L50 DS3/E3 Framer IC consists of a
Transmit section, Receiver section, Performance
Monitor Section and a Microprocessor interface.
The Transmit Section includes a Transmit Payload
Data Input Interface, a Transmit Overhead data Input
Interface Section, a Transmit HDLC Controller, a
Transmit DS3/E3 Framer block and a Transmit LIU In-
terface Block which permits the Terminal Equipment
to transmit data to a remote terminal.
The Receive Section consists of a Receive LIU Inter-
face, a Receive DS3/E3 Framer, a Receive HDLC
Controller, a Receive Payload Data Output Interface,
and a Receive Overhead Data Interface which allows
the local terminal equipment to receive data from re-
mote terminal equipment.
The Microprocessor Interface is used to configure the
Framer IC in different operating modes and monitor
the performance of the Framer.
The Performance Monitor Sections consist of a large
number of Reset-upon-Read and Read-Only regis-
ters that contain cumulative and one-second statistics
that reflect the performance/health of the Framer IC/
system.
FEATURES
• Transmits, Receives and Processes data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.
• 1 Channel HDLC Controller - Tx and Rx
• Interfaces to all Popular Microprocessors
• Integrated Framer Performance Monitor
• Available in a 100 Pin PQFP package
• 3.3V Power Supply with 5V Tolerant I/O
• Operating Temperature -40°C to +85°C
APPLICATIONS
• Network Interface Units
• CSU/DSU Equipment.
• PCM Test Equipment
• Fiber Optic Terminals
• DS3/E3 Frame Relay Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT72L50
TRST
T es tM ode
NibIntf
T xO H E n able
T xO H C lk
T xO H F ra m e
T xA I S E n
T xO H
T xO H Ins
T xL ine C l k
T xP O S
T xN E G
RxLineClk
RxPOS
RxNEG
E xtLO S
RxOHEnable
R xO H C lk
RxOH
RxRed
RxOHFram e
RxOOF
T3/E3
Transm it
Overhead
Interface
LIU
Interface/
Controller
T3/E3
Receive
Overhead
Interface
T3/E3 Transmit
Fram er
T3/E3
transm it
Input
T3 FEAC & Data
Link Controller
Perform ance
Monitor
Interrupt
Controller
T3/E3 Receive
Fram er
T3/E3
Receive
Output
HDLC
controller
µP
Interface
HDLC
controller
T xO H Ind
T xN ibF ra m e
TxFram e
T xN ibC lk
T xL nC lk
TxFram eRef
T xN ib
T xS e r
A[8:0]
D[7:0]
ALE_AS
W R_R/W
CS
RDY_DTCK
Reset
Int
MOTO
RD_DS
R xC lk
RxOHind
RxFram e
R xN ib
RxSer
R xO utC lk
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

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XRT72L50 pdf
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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
2.3.5.5 Transmit DS3 LAPD Status and Interrupt Register ....................................................................... 87
2.3.5.6 Transmit DS3 M-Bit Mask Register ............................................................................................... 88
2.3.5.7 Transmit DS3 F-Bit Mask Register 1 ............................................................................................. 89
2.3.5.8 Transmit DS3 F-Bit Mask Register 2 ............................................................................................. 89
2.3.5.9 Transmit F-Bit Mask Register 3 ..................................................................................................... 89
2.3.5.10 Transmit F-Bit Mask Register 4 ................................................................................................... 90
2.3.6 Transmit E3 (ITU-T G.832) Configuration Registers ............................................................................... 90
2.3.6.1 Transmit E3 Configuration Register (E3, ITU-T G.832) ................................................................ 90
2.3.6.2 Transmit E3 LAPD Configuration Register (E3, ITU-T G.832) ...................................................... 91
2.3.6.3 Transmit E3 LAPD Status and Interrupt Register (E3, ITU-T G.832) ............................................ 92
2.3.6.4 Transmit E3 GC Byte Register (E3, ITU-T G.832) ........................................................................ 93
2.3.6.5 Transmit E3 MA Byte Register (E3, ITU-T G.832) ........................................................................ 93
2.3.6.6 Transmit E3 NR Byte Register (E3, ITU-T G.832) ........................................................................ 94
2.3.6.7 Transmit E3 TTB-0 Register (E3, ITU-T G.832) ............................................................................ 94
2.3.6.8 Transmit E3 TTB-1 Register (E3, ITU-T G.832) ............................................................................ 95
2.3.6.9 Transmit E3 TTB-2 Register (E3, ITU-T G.832) ............................................................................ 95
2.3.6.10 Transmit E3 TTB-3 Register (E3, ITU-T G.832) .......................................................................... 96
2.3.6.11 Transmit E3 TTB-4 Register (E3, ITU-T G.832) .......................................................................... 96
2.3.6.12 Transmit E3 TTB-5 Register (E3, ITU-T G.832) .......................................................................... 96
2.3.6.13 Transmit E3 TTB-6 Register (E3, ITU-T G.832) .......................................................................... 97
2.3.6.14 Transmit E3 TTB-7 Register (E3, ITU-T G.832) .......................................................................... 97
2.3.6.15 Transmit E3 TTB-8 Register (E3, ITU-T G.832) .......................................................................... 98
2.3.6.16 Transmit E3 TTB-9 Register (E3, ITU-T G.832) .......................................................................... 98
2.3.6.17 Transmit E3 TTB-10 Register (E3, ITU-T G.832) ........................................................................ 98
2.3.6.18 Transmit E3 TTB-11 Register (E3, ITU-T G.832) ........................................................................ 99
2.3.6.19 Transmit E3 TTB-12 Register (E3, ITU-T G.832) ........................................................................ 99
2.3.6.20 Transmit E3 TTB-13 Register (E3, ITU-T G.832) ...................................................................... 100
2.3.6.21 Transmit E3 TTB-14 Register (E3, ITU-T G.832) ...................................................................... 100
2.3.6.22 Transmit E3 TTB-15 Register (E3, ITU-T G.832) ...................................................................... 100
2.3.6.23 Transmit E3 FA1 Byte Error Mask Register (E3, ITU-T G.832) ................................................ 101
2.3.6.24 Transmit E3 FA2 Byte Error Mask Register (E3, ITU-T G.832) ................................................ 101
2.3.6.25 Transmit E3 BIP-8 Error Mask Register (E3, ITU-T G.832) ...................................................... 101
2.3.6.26 TxE3 SSM Register - G.832 ..................................................................................................... 102
2.3.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ................................................................ 102
2.3.7.1 Transmit E3 Configuration Register (ITU-T G.751) ..................................................................... 102
2.3.7.2 Transmit E3 LAPD Configuration Register (ITU-T G.751) .......................................................... 104
2.3.7.3 Transmit E3 LAPD Status and Interrupt Register (ITU-T G.751) ................................................ 104
2.3.7.4 Transmit E3 Service Bits Register (ITU-T G.751) ....................................................................... 105
2.3.7.5 Transmit E3 FAS Mask Register - 0 (ITU-T G.751) .................................................................... 106
2.3.7.6 Transmit E3 FAS Error Mask Register - 1 (ITU-T G.751) ........................................................... 106
2.3.7.7 Transmit E3 BIP-4 Error Mask Register (ITU-T G.751) .............................................................. 106
2.3.8 Performance Monitor Registers ............................................................................................................. 107
2.3.8.1 PMON Line Code Violation Count Register - MSB ..................................................................... 107
2.3.8.2 PMON Line Code Violation Count Register - LSB ...................................................................... 107
2.3.8.3 PMON Framing Bit/Byte Error Count Register - MSB ................................................................. 107
2.3.8.4 PMON Framing Bit/Byte Error Count Register - LSB .................................................................. 108
2.3.8.5 PMON Parity Error Count Register - MSB .................................................................................. 108
2.3.8.6 PMON Parity Error Count Register - LSB ................................................................................... 108
2.3.8.7 PMON FEBE Event Count Register - MSB ................................................................................. 109
2.3.8.8 PMON FEBE Event Count Register - LSB .................................................................................. 109
2.3.8.9 PMON CP-Bit Error Event Count Register - MSB ....................................................................... 109
2.3.8.10 PMON CP-Bit Error Event Count Register - LSB ...................................................................... 110
2.3.8.11 PRBS Error Count Register - MSB ........................................................................................... 110
2.3.8.12 PRBS Error Count Register - LSB ............................................................................................ 110
2.3.8.13 PMON Holding Register ........................................................................................................... 111
2.3.8.14 One-Second Error Status Register ........................................................................................... 111
2.3.8.15 One-Second Line Code Violation Accumulator Register - MSB ............................................... 111
2.3.8.16 One-Second Line Code Violation Accumulator Register - LSB ................................................ 112
2.3.8.17 One-Second Frame Parity Error Accumulator Register - MSB ................................................. 112
III

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XRT72L50 arduino
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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
Figure 117. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data ........... 291
TABLE 56: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE
TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ........................................................... 291
Figure 118. Interfacing the XRT72L50 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................ 292
Figure 119. Illustration of AMI Line Code ................................................................................................................... 292
Figure 120. Illustration of two examples of HDB3 Decoding ....................................................................................... 293
TABLE 57: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE
SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................................................... 294
Figure 121. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the rising edge of RxLineClk .................................................................................................... 294
5.3.2 The Receive E3 Framer Block .............................................................................................................. 295
Figure 122. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the falling edge of RxLineClk ................................................................................................... 295
Figure 123. The Receive E3 Framer Block and the Associated Paths to Other Functional Blocks ............................ 295
5.3.2.1 The Framing Acquisition Mode ................................................................................................... 296
Figure 124. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Algorithm 297
Figure 125. Illustration of the E3, ITU-T G.751 Framing Format ................................................................................. 297
5.3.2.2 The Framing Maintenance Mode ................................................................................................ 299
5.3.2.3 Forcing a Reframe via Software Command ................................................................................ 300
5.3.2.4 Performance Monitoring of the Frame Synchronization Section, within the Receive E3 Framer block
301
5.3.2.5 The RxOOF and RxLOF output pin. ........................................................................................... 301
TABLE 58: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE FRAMING STATE
OF THE RECEIVE E3 FRAMER BLOCK .............................................................................................................. 301
5.3.2.6 E3 Receive Alarms ..................................................................................................................... 302
5.3.2.7 The Loss of Signal (LOS) Alarm ................................................................................................. 302
5.3.2.8 The AIS (Alarm Indication Status) Condition .............................................................................. 303
5.3.2.9 The Far-End-Receive Failure (FERF) Condition ......................................................................... 304
5.3.2.10 Error Checking of the Incoming E3 Frames .............................................................................. 305
Figure 126. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with a
correct BIP-4 Value. ..................................................................................................................................... 306
Figure 127. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
A bit set to “0” .............................................................................................................................................. 307
Figure 128. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with an
incorrect BIP-4 value. .................................................................................................................................. 308
Figure 129. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
A bit-field set to “1” ...................................................................................................................................... 308
5.3.3 The Receive HDLC Controller Block ..................................................................................................... 310
Figure 130. LAPD Message Frame Format ................................................................................................................ 311
TABLE 59: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MESSAGE TYPE/SIZE
314
5.3.4 The Receive Overhead Data Output Interface ...................................................................................... 316
Figure 131. Flow Chart depicting the Functionality of the LAPD Receiver ................................................................. 316
5.3.4.1 Method 1 - Using the RxOHClk Clock signal .............................................................................. 317
Figure 132. The Receive Overhead Output Interface block ........................................................................................ 317
Figure 133. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 1) . 318
TABLE 60: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(FOR METHOD 1) ........................................................................................................................................... 318
TABLE 61: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST
SAMPLED "HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN .................... 319
Figure 134. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method 1). ..... 319
TABLE 62: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(METHOD 2) .................................................................................................................................................. 320
Figure 135. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 2) . 321
TABLE 63: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME WAS LAST SAMPLED
"HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN .................................. 321
5.3.5 The Receive Payload Data Output Interface ......................................................................................... 322
Figure 136. Illustration of the signals that are output via the Receive Overhead Data Output Interface block (for Method 2).
322
Figure 137. The Receive Payload Data Output Interface block .................................................................................. 322
TABLE 64: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
323
5.3.5.1 Serial Mode Operation Behavior of the XRT72L50 ..................................................................... 324
Figure 138. The Terminal Equipment being interfaced to the Receive Payload Data Input Interface Block (Serial Mode
IX

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