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PDF XRT7250 Data sheet ( Hoja de datos )

Número de pieza XRT7250
Descripción DS3/E3 FRAMER IC
Fabricantes Exar Corporation 
Logotipo Exar Corporation Logotipo



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XRT7250
MARCH 2001
DS3/E3 FRAMER IC
REV. 1.1.1
GENERAL DESCRIPTION
The XRT7250 DS3/E3 Framer IC is designed to ac-
cept “User Data” from the Terminal Equipment and in-
sert this data into the “payload” bit-fields within an
“outbound” DS3/E3 Data Stream. Further, the Framer
IC is also designed to receive an “inbound” DS3/E3
Data Stream (from the Remote Terminal Equipment)
and extract out the “User Data”.
The XRT7250 DS3/E3 Framer is designed to support
full-duplex data flow between Terminal Equipment
and an LIU (Line Interface Unit) IC. The Framer De-
vice will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 Framing Formats.
The XRT7250 DS3/E3 Framer IC consists of four sec-
tions.
The Transmit Section, includes a Transmit Payload
Data Input Interface, a Transmit Overhead data Input
Interface Section, a Transmit HDLC Controller, a
Transmit E3/DS3 Framer block and a Transmit LIU In-
terface Block which permits the Terminal Equipment
to transmit data to a remote terminal.
The Receive Section, consists of a Receive LIU Inter-
face, a Receive E3/DS3 Framer, a Receive HDLC
Controller, a Receive Payload Data Output Interface,
and a Receive Overhead Data Interface which allows
the local terminal equipment to receive data from re-
mote terminal equipment.
The Microprocessor Interface is used to configure the
Framer IC in different operating modes and monitor
the performance of the Framer.
The Performance Monitor Section consists of a large
number of "Reset-upon-Read" and "Read-Only" reg-
isters that contain cumulative and "one-second" sta-
tistics that reflect the performance/health of the Fram-
er IC/system.
FEATURES
Transmits, Receives and Processes data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.
Interfaces to all Popular Microprocessors
Integrated Framer Performance Monitor
Available in a 100 Pin PQFP package
Operating Temperature -40°C to +85°C
APPLICATIONS
Interface to DS3 or E3 Networks
CSU/DSU Equipment.
PCM Test Equipment
Fiber Optic Terminals
BLOCK DIAGRAM OF XRT7250
TxOHFrame
TxOHEnable
TxOH
TxOHClk
TxOHIns
TxOHInd
TxSer
TxNib[3:0]
TxInClk
TxNibClk
TxFrame
MOTO
D[7:0]
A[8:0]
Int
CS
Rd_DS
Wr_RW
Rdy_Dtck
Reset
ALE_AS
RxSer
RxNib[3:0]
RxOutClk
RxNibClk
RxFrame
RxOHFrame
RxOH
RxOHClk
RxOHEnable
Transmit Overhead
Input
Interface Block
Transmit
Payload Data
Input
Interface Block
Transmit DS3/E3
Framer Block
Microprocessor
Interface
Tx LAPD Buffer/
Controller
Rx LAPD Buffer/
Controller
Receive Payload
Data Output
Interface Block
Receive Overhead
Output
Interface Block
Receive DS3/E3
Framer Block
Transmit LIU
Interface
Block
TxPOS
TxNEG
TxLineClk
Receive LIU
Interface
Block
RxPOS
RxNEG
RxLineClk
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XRT7250 pdf
XRT7250 DS3/E3 FRAMER IC
áç
REV. 1.1.1
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................... 100
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ........................................................ 102
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................... 102
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) ........................................................................ 103
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ............................................................ 103
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ............................................................ 104
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) .............................................................. 104
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51) ................................................... 105
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ....................... 105
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) ........................ 105
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ........................................... 105
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ............................................ 106
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56) ................................................ 106
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57) ................................................. 106
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58) ............................................. 107
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59) .............................................. 107
PMON HOLDING REGISTER (ADDRESS = 0X6C) .............................................................................. 107
ONE-SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D) ..................................................... 108
LCV - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X6E) ................................ 108
LCV - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X6F) ................................. 108
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X70) ....
109
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X71) .....
109
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X72) .....
109
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73) .....
109
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) .................................................................. 110
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ................................................................... 112
2.4 THE LOSS OF CLOCK ENABLE FEATURE ......................................................................................... 112
ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER ..................................................................... 113
2.5 USING THE PMON HOLDING REGISTER .......................................................................................... 113
2.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER MICROPROCESSOR INTERFACE SECTION ............. 113
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) .......................................................... 115
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................... 116
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................... 118
2.7 INTERFACING THE FRAMER TO AN INTEL-TYPE MICROPROCESSOR .................................................... 118
2.8 INTERFACING THE FRAMER IC TO A MOTOROLA-TYPE MICROPROCESSOR ........................................ 121
3.0 THE LINE INTERFACE AND SCAN SECTION .............................................................................. 122
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE REGISTER .............................................................. 123
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) .................................................................. 123
3.2 BIT-FIELDS WITHIN THE LINE INTERFACE SCAN REGISTER ............................................................... 125
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ................................................................... 126
XRT7250 CONFIGURATION .......................................................................................... 127
4.0 DS3 OPERATION OF THE XRT7250 ............................................................................................. 127
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................... 127
4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS .......................................... 127
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................... 128
4.2 THE TRANSMIT SECTION OF THE XRT7250 (DS3 MODE OPERATION) ............................................. 131
III

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XRT7250 arduino
XRT7250 DS3/E3 FRAMER IC
áç
REV. 1.1.1
7.0 DIAGNOSTIC OPERATION OF THE XRT7250 FRAMER IC ........................................................ 441
ORDERING INFORMATION ..................................................................................... 443
PACKAGE DIMENSIONS ......................................................................................... 443
REVISION HISTORY ............................................................................................................................. 444
IX

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