|
|
PDF XRD98L61 Data sheet ( Hoja de datos )
| Número de pieza | XRD98L61 | |
| Descripción | CCD Image Digitizers | |
| Fabricantes | Exar | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XRD98L61 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
XRD98L61
CCD Image Digitizers with
CDS, PGA and 12-Bit A/D
FEATURES
• 12-Bit Resolution ADC
• 20MHz Sampling Rate
• 10-Bit Programmable Gain: 0dB to 36dB PGA
• Digitally Controlled Offset-Calibration with Pixel
Averager and Hot Pixel Clipper
• Widest Black Level Calibration Range at
Maximum Gain
• DNS Filter Removes Black Level Digital Noise
• Manual Control of Offset DAC via Serial Port for
use with High-speed Scanners
• 1ns/step Programmable Aperture Delay on SPIX,
SBLK and ADCLK Sampling Clocks
• Single 2.7V to 3.6V Power Supply
• Optimized Power Consumption down to 125mW
with External Resistor
• Low Power for Battery Operation
• Two Serially Controlled 8-Bit D/A Converters
May 2001-2
• 0.1mA Stand-by Mode Current
• Three-state Digital Outputs
• 2,000V ESD Protection
• 48-Pin TQFP Package
APPLICATIONS
• Mega-pixel Digital Still Cameras
• Digital Camcorders
• 3-CCD Professional/Broadcast Camera
• Line Scan Cameras
• PC Video Cameras
• CCTV/Security Cameras
• Industrial/Medical Cameras
• 2D Bar Code Readers
• High Speed Scanners
• Digital Copiers
GENERAL DESCRIPTION
The XRD98L61 is a complete, low power CCD Image
Digitizer for digital motion and still cameras. The
product includes a high bandwidth differential Corre-
lated Double Sampler (CDS), 10-bit digitally Program-
mable Gain Amplifier (PGA), 12-bit Analog-to-Digital
Converter (ADC) and improved digitally controlled
black level auto-calibration circuitry with program-
mable pixel averager, hot pixel clipper, and a DNS
filter.
Two 8-bit serial controlled digital-to-analog converter
(DACs) are provided to control external analog signals
(Iris, Focus, Flash, etc.)
The Correlated Double Sampler (CDS) subtracts the
CCD output signal black level from the video level.
Common mode signal and power supply noise are
rejected by the differential CDS input stage.
ORDERING INFORMATION
The PGA is digitally controlled with 10-bit resolution on
a linear dB scale, resulting in a gain range of 0dB to
36dB with 0.047dB per LSB of the gain code.
The auto calibration circuit compensates for any inter-
nal offset of the XRD98L61 as well as black level offset
from the CCD.
The PGA and black level auto-calibration are con-
trolled through a simple 3-wire serial interface. The
timing circuitry is designed to enable users to select a
wide variety of available CCD and image sensors for
their applications. Readback of the serial data regis-
ters is available from the digital output bus.
The XRD98L61 has direct access to the ADC and
PGA inputs for digitizing other analog signals.
The XRD98L61 is packaged in 48-lead TQFP to reduce
space and weight, and is suitable for hand-held and
portable applications.
Part No.
XRD98L61AIV
Package Temperature Range
48-Pin TQFP
-40°C to 85°C
Operating
Power Supply
3.0V
Maximum
Sampling Rate
20 MSPS
Rev. 2.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRD98L61
DC ELECTRICAL CHARACTERISTICS - XRD98L61 (CONT'D)
Unless otherwise specified: OVDD = DVDD =AVDD = 3.0V, Pixel Rate = 20MSPS, TA = 25°C
Rext= 30KOhm
Symbol Parameter
Min. Typ. Max. Unit Conditions
System Specifications
DNLS
en MAXAV
en MINAV
Latency
System DNL
Input Referred Noise, Max.Gain
Input Referred Noise, Min.Gain
Pipeline Delay
-1.0
+0.75 +1.0 LSB No missing codes, monotonic
180 µVrms Gain Code = 768 (36db)
800 µVrms Gain Code = 0 (0dB)
7.5 cycles
Digital Inputs (Digital Input Thresholds are Set by DVDD)
VIH Digital Input High Voltage
2.5
V
VIL Digital Input Low Voltage
0.5 V
IIH Input Leakage, P/D & Reset
20 40 100 µA Input = VDD
IIH Input Leakage, OE
-.50 0 .50 µA Input = VDD
IIL
Input Leakage, P/D & Reset
-.50 0 .50 µA Input = GND
IIL Input Leakage, OE
-40 -5 0 µA Input = GND
IIL / IIH
Input Leakage, All Other Inputs -100 10 100 nA Input = VDD or GND
CIN Input Capacitance
5 pF
Digital Outputs
VOH
VOL
IOZ
Digital Output High Voltage
Digital Output Low Voltage
High–Z Leakage
OVDD-0.5
-1
V While sourcing 2mA
0.5 V While sinking 2mA
+1 µA OE = 0 or PD = 1
Rev. 2.00
5
5 Page 
XRD98L61
Calibration
Default
D9
Avg[2]
1
D8
Avg[1]
0
D7
Avg[0]
1
D6
Mode
0
D5 D4 D3 D2
LFrame DNS[1] DNS[0] FastCal
0111
D1
Hold
0
D0
ManCal
0
Calibration Register (Reg. 2, Address 000010)
The Calibration register is used to set various options for the Black Level Offset Calibration.
Avg[2:0] set the number of OB pixels to average:
000 = 4 pixels (not recommended)
100 = 64 pixels
001 = 8 pixels (not recommended)
010 = 16 pixels (not recommended)
101 = 128 pixels (default)
110 = 256 pixels
011 = 32 pixels
111 = 512 pixels
Mode=0, selects Line mode calibration (use OB pixels at start or end of each line).
Mode=1, do not use.
LFrame=0, selects Line mode calibration.
LFrame=1, do not use.
DNS[1:0] selects the Digital Noise Suppression filter setting:
00 = off,
10 = medium,
01 = narrow,
11 = wide.
FastCal=0, disables speedup convergence option of the calibration feedback loop.
FastCal=1, enables an option to speedup convergence of the calibration feedback loop.
Hold=0, normal operation of calibration feedback loop.
Hold=1, stops all updates to the Coarse and Fine offset DAC accumulators.
ManCal=0, normal operation of calibration feedback loop.
ManCal=1, enables manual calibration. The offset DACs are set to the values in the CDAC and FDAC registers.
See the Black Level Offset Calibration section for more information.
WaitA
Default
D9
WL[11]
0
D8
WL[10]
0
D7 D6
WL[9] WL[8]
00
WaitA Register (Reg. 3, Address 000011)
D5
WL[7]
0
D4
WL[6]
0
D3
WL[5]
0
D2
WL[4]
0
D1
WL[3]
0
D0
WL[2]
0
WaitB
Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WL[1] WL[0]
0000000001
WaitB Register (Reg. 4, Address 000100)
The WaitA and WaitB registers are concatenated to make up the Wait register.
See OB Pixel calibration section for more information.
OB Lines
Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OBL[7] OBL[6] OBL[5] OBL[4] OBL[3] OBL[2] OBL[1] OBL[0]
0000000010
OB Lines Register (Reg. 5, Address 000101)
The OB Lines register is used by the Offset Calibration Logic to set the number of Optical Black lines used
for Calibration in the Frame Mode. Do not use.
Rev. 2.00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRD98L61.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XRD98L61 | CCD Image Digitizers | Exar |
| XRD98L62 | CCD Image Digitizers | Exar |
| XRD98L63 | CCD Image Digitizers with CDS/ PGA and 12-Bit A/D |  Exar Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |