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PDF XRD9814 Data sheet ( Hoja de datos )

Número de pieza XRD9814
Descripción (XRD9814 / XRD9816) 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors
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XRD9814/XRD9816
3-Channel 14/16-Bit Linear
CCD/CIS Sensor Signal Processors
FEATURES
14-Bit (XRD9814) or 16-Bit (XRD9816)
A/D Converter
No Missing Codes
Triple-Channel, 2.5 MSPS Color Scan Mode
Single-Channel, 6 MSPS Monochrome Scan
Mode
Triple Correlated Double Sampler
Triple 10-Bit Programmable Gain Amplifier
Triple 10-Bit Offset Compensation DAC
Fully Differential or Single-Ended Inputs
CDS or S/H Mode
Inverting or Non-Inverting Mode
Internal Voltage Reference
Serial Control: On Data Bus or Separate Pins
December 1999-2
14-Bit or 8-Bit (Nibble) Parallel Data Output
(XRD9814)
16-Bit or 8-Bit (Nibble) Parallel Data Output
(XRD9816)
5V Operation and 3V I/O Compatibility
Low Power CMOS: 500mW @ 5V
APPLICATIONS
48-Bit Color Scanners (XRD9816)
42-Bit Color Scanners (XRD9814)
CCD or CIS Color Imagers
Gray Scale Scanners
Film Scanners
GENERAL DESCRIPTION
The XRD9814/9816 is a fully integrated, high-perfor-
mance analog signal processor/digitizer specifically
designed for use in 3-channel linear Charge Coupled
Device (CCD) and Contact Image Sensitive (CIS)
imaging applications.
Each channel of the XRD9814/9816 includes a Corre-
lated Double Sampler (CDS), Programmable Gain
Amplifier (PGA) and channel offset adjustment. After
gain and offset adjustment, the analog inputs are
sequentially sampled and digitized by an accurate 14/
16-bit A/D converter. The analog front-end can be
configured for inverting/non-inverting input, CDS or
sample-hold (S/H) mode, or AC/DC coupling,
making the XRD9814/9816 suitable for use in CCD,
CIS and other data acquisition applications.
The CDS mode of operation supports both line and
pixel-clamp modes and can be used to achieve signifi-
cant reduction in system 1/f noise and CCD reset
clock feed-through. In S/H mode the internal DC-
restore voltage clamp can be enabled or disabled to
support AC-coupled or DC inputs. Sampling mode,
10-bit PGA gain (1024 linear steps), 8-bit fine offset
adjustment (256 linear steps), 2-bit gross offset adjust-
ment and input signal polarity are all programmable
through a serial interface. PGA gain range is 1 to 10,
and channel offset range is -300mV to 300mV for fine
adjustment and additional -400mV to +200mV for
gross offset adjustment. The A/D Full-Scale Range
(FSR) is programmable to 2V or 3V.
ORDERING INFORMATION
Part No.
XRD9814ACV
XRD9816ACV
Package Type
48-Lead TQFP
48-Lead TQFP
Temperature Range
0°C to +70°C
0°C to +70°C
Rev. 1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XRD9814 pdf
XRD9814/9816
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
2
3
4
5
6
7
8
9
10
11
AVDD3 12
XRD9816
36 INSEL
35 ADCCLK
34 BSAMP
33 VSAMP
32 LCLMP
31 AVDD1
30 AGND1
29 SGND
28 CAPN
27 CAPP
26 CREF
25 TEST2
13 14 15 16 17 18 19 20 21 22 23 24
Note:
Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD3
AV
DD2
AGND2
RED(+)
Description
Data Output Bit 10
Data Output Bit9
Data Output Bit 8
Data Output Bit 7
Data Output Bit 6
Data Output Bit 5
Data Output Bit 4
Data Output Bit 3
Data Output Bit 2
Data Output Bit 1
Data Output Bit 0
Analog Power Supply
Analog Power Supply
Analog Ground (Substrate)
Red Positive Analog Input
Rev. 1.00
5

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XRD9814 arduino
XRD9814/9816
Function
A2
Configuration Reg #1
Configuration Reg #2
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
0
0
0
0
1
1
1
1
A1 A0 PB9-PB0
00
01
10
11
00
01
10
11
See Configuration Register #1
See Configuration Register #2
10-Bit Gain
10-Bit Gain
10-Bit Gain
2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
Table 1. XRD9814/9816 Register Overview
A2 A1 A0
Address
00 0
Bit
Assignment
PB9 Single Channel
Power Save Mode
PB8 Digital Reset
PB7 PB6
Clamp Mode
PB5 A/D Full Scale Range
PB4 PB3
Color Select
PB2
Input Signal Polarity
PB1
Input Buffer Enable
PB0
VSAMP Timing
PB9-PB0 Bit Definition
0 Unused channels are powered down to 0
save power (single channel mode only)
1 Unused channels are powered up
0 No Reset
1 Resets all registers to the default configuration
00 CDS pixel
01 CDS line clamp
10 No clamp
11 S/H line clamp
0 2Vpp Full Scale
1 3Vpp Full Scale (recommended for better performance)
00 RGB 3 channel color mode
01 Red single channel mode
10 Green single channel mode
11 Blue single channel mode
0 Inverted for CCD or negative going signals
1 Non-inverted for CIS or positive going signals
0 No buffer (DC coupled or AC coupled inputs
with pixel clamp mode
1 Buffer enabled (AC Coupled inputs for line clamp or no
clamp mode
0 Timing option #1 (see Figure 3, 4, 7 & 8 for details)
1 Timing option #2 (see Figure 3, 4, 7 & 8 for details)
Table 2. Configuration Register #1 Definition (Default Configuration is 000H)
Rev. 1.00
11

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