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PDF XR20M1172 Data sheet ( Hoja de datos )
| Número de pieza | XR20M1172 | |
| Descripción | TWO CHANNEL I2C/SPI UART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
JUNE 2007
REV. 1.0.0
GENERAL DESCRIPTION
The XR20M11721 (M1172) is a high performance two
channel universal asynchronous receiver and
transmitter (UART) with 64 byte TX and RX FIFOs
and a selectable I2C/SPI slave interface. The M1172
operates from 1.62 to 3.63 volts. The standard
features include 16 selectable TX and RX FIFO
trigger levels, automatic hardware (RTS/CTS) and
software (Xon/Xoff) flow control, and a complete
modem interface. Onboard registers provide the user
with operational status and data error flags. An
internal loopback capability allows system
diagnostics. Additional enhanced features includes a
programmable fractional baud rate generator and 8X
and 4X sampling rate that allows for a maximum baud
rate of 16 Mbps at 3.3V. The M1172 is available in the
32-pin QFN and 28-pin TSSOP packages. The 32-
pin QFN package has the EN485# and ENIR# pins to
allow the UART to power-up in the Auto RS485 mode
or the Infrared mode.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Battery-Operated Devices
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 1.62 to 3.6 Volt Operation
• Selectable I2C/SPI Interface
• Full-featured UART
■ Data rate of up to 16 Mbps at 3.3 V
■ Data rate of up to 12.5 Mbps at 2.5 V
■ Data rate of up to 8 Mbps at 1.8 V
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 64 bytes
■ 16 Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Halt and Resume Transmission Control
■ Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■ Wireless Infrared (IrDA 1.0 and 1.1) Encoder/
Decoder
■ Automatic sleep mode (< 30 uA at 3.3V)
■ General Purpose I/Os
■ Full modem interface
• Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
• 32-QFN and 28-TSSOP packages
FIGURE 1. XR20M1172 BLOCK DIAGRAM
VCC
EN IR#
E N 485#
IR Q #
RESET#
SDA
SCK
A 0/ C S #
A1/SI
SO
I2C/ S P I#
1.62 V – 3.63V
I2 C / S P I
Interface
C rystal
Osc /
B u ffe r
Channel 1
UART
Regs
64 Byte
TX FIFO
64 Byte
RX FIFO
BRG
G PIO s
UART Channel 2
(S im ilar to C hannel1)
TXA
RXA
RTSA#
CTSA#
G P IO [7:0]
TXB
RXB
RTSB#
CTSB#
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.0
Pin Description
XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
NAME
GPIO7/RIA#
VCC
A0/CS#
A1/SI
I2C/SPI#
-
NC
32-QFN
PIN #
28
29
30
31
32
PAD
1, 8
28-TSSOP
PIN#
TYPE
DESCRIPTION
28 I/O General purpose I/O pin or UART Ring-Indicator. If this pin is an input
and is unused, it should be connected to VCC or GND. If this pin is an
output and is unused, it should be left unconnected. See IOControl[1]
and IODir register.
1 Pwr 1.62V to 3.63V power supply.
2 I I2C-bus device address select A0 or SPI chip select. If I2C-bus config-
uration is selected, this pin along with the A1 pin allows user to change
the device’s base address. If SPI configuration is selected, this pin is
the SPI chip select pin (Schmitt-trigger, active LOW).
3 I I2C-bus device address select A1 or SPI data input pin. If I2C-bus
onfiguration is selected, this pin along with A0 pin allows user to
change the device’s base address. If SPI configuration is selected,
this pin is the SPI data input pin.
4 I I2C-bus or SPI interface select. I2C-bus interface is selected if this pin
is HIGH. SPI interface is selected if this pin is LOW
- Pwr The center pad on the backside of the QFN package is metallic and is
not electrically connected to anything inside the device. It must be sol-
dered on to the PCB and may be optionally connected to GND on the
PCB. The thermal pad size on the PCB should be the approximate
size of this center pad and should be solder mask defined. The solder
mask opening should be at least 0.0025" inwards from the edge of the
PCB thermal pad.
- - No Connection.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
REV. 1.0.0
FIGURE 10. SPI FIFO READ
SCLK
XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
R/W A3 A2 A1 A0 CH1 CH0 X
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
last bit
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
2.2 Device Reset
The RESET# input resets the internal registers and the serial interface outputs in the UART to its default state
(see Table 16). An active low pulse of longer than 40 ns duration will be required to activate the reset function
in the device.
2.3 Internal Registers
The M1172 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to the industry standard ST16C550. These registers function as data
holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR),
receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR),
programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible Scratchpad Register
(SPR).
Beyond the general 16C550 features and capabilities, the M1172 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR, TXLVL, RXLVL, IODir, IOState, IOIntEna, IOControl, EFCR and DLD) that
provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, automatic RS-485 half-
duplex direction output enable/disable, TX and RX FIFO level counters, and programmable FIFO trigger level
control. For complete details, see “Section 3.0, UART Internal Registers” on page 24.
2.4 IRQ# Output
The IRQ# interrupt output changes according to the operating mode and enhanced features setup. Table 4
and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 21 through 35.
TABLE 4: IRQ# PIN OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
IRQ# Pin
NO
HIGH = a byte in THR
HIGH = FIFO above trigger level
LOW = THR empty
LOW = FIFO below trigger level or FIFO empty
IRQ# Pin
YES
HIGH = a byte in THR
LOW = transmitter empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or transmitter empty
IRQ# Pin
TABLE 5: IRQ# PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
HIGH = no data
LOW = 1 byte
HIGH = FIFO below trigger level
LOW = FIFO above trigger level
11
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| PDF Descargar | [ Datasheet XR20M1172.PDF ] | |
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