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PDF XR20M1170 Data sheet ( Hoja de datos )
| Número de pieza | XR20M1170 | |
| Descripción | I2C/SPI UART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR20M1170
I2C/SPI UART WITH 64-BYTE FIFO
JULY 2012
REV. 1.1.0
GENERAL DESCRIPTION
The XR20M11701 (M1170) is a high performance
universal asynchronous receiver and transmitter
(UART) with 64 byte TX and RX FIFOs and a
selectable I2C/SPI slave interface. The M1170
operates from 1.62 to 3.63 volts. The enhanced
features in the M1170 include a programmable
fractional baud rate generator, an 8X and 4X
sampling rate that allows for a maximum baud rate of
16 Mbps at 3.3V. The standard features include 16
selectable TX and RX FIFO trigger levels, automatic
hardware (RTS/CTS) and software (Xon/Xoff) flow
control, and a complete modem interface. Onboard
registers provide the user with operational status and
data error flags. An internal loopback capability
allows system diagnostics. The M1170 is available in
the 24-pin QFN, 16-pin QFN, 24-pin TSSOP and 16-
pin TSSOP packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Battery-Operated Devices
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 1.62 to 3.6 Volt Operation
• Selectable I2C/SPI Interface
• SPI clock frequency up to
■ 18 MHz at 3.3 V
■ 16 MHz at 2.5 V
■ 8 MHz at 1.8 V
• Full-featured UART
■ Data rate of up to 16 Mbps at 3.3 V
■ Data rate of up to 12.5 Mbps at 2.5 V
■ Data rate of up to 8 Mbps at 1.8 V
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 64 bytes
■ 16 Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Halt and Resume Transmission Control
■ Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■ Wireless Infrared (IrDA 1.0 and 1.1) Encoder/
Decoder
■ Automatic sleep mode (< 15 uA at 3.3V)
■ General Purpose I/Os
■ Full modem interface
• Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
• 24-QFN, 16-QFN, 24-TSSOP, 16-TSSOP
packages
FIGURE 1. XR20M1170 BLOCK DIAGRAM
VCC
IRQ#
SDA
SCL
A0/CS#
A1/SI
SO
I2C/SPI#
1.62V – 3.63V
I2C/SPI
Interface
UART
Regs
64 Byte
TX FIFO
64 Byte
RX FIFO
BRG
GPIOs
Crystal Osc/Buffer
TX
RX
RTS#
CTS#
GPIO[7:0]
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XR20M1170
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR20M1170 (M1170) integrates a selectable I2C/SPI bus interface with an enhanced Universal
Asynchronous Receiver and Transmitter (UART). The configuration registers set is 16550 UART compatible
for control, status and data transfer. Additionally, the M1170 has 64-bytes of transmit and receive FIFOs,
automatic RTS/CTS hardware flow control, automatic Xon/Xoff and special character software flow control,
programmable transmit and receive FIFO trigger levels, infrared encoder and decoder (IrDA 1.0 and 1.1),
programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps
with 4X sampling clock rate. The XR20M1170 is a 1.62V to 3.63V device. The M1170 is fabricated with an
advanced CMOS process.
Enhanced Features
The M1170 UART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the industry standard 16C550. The M1170 is designed to work with low supply voltage and high
performance data communication systems, that require fast data processing time. Increased performance is
realized in the M1170 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow
control mechanism. This allows the external processor to handle more networking tasks within a given time.
For example, the 16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses
a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to
service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the M1170, the data buffer will
not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the
programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
The M1170 supports a half-duplex output direction control signaling pin, RTS#, to enable and disable the
external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive
state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic
state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set EFCR bit-4 to “1”. This pin is HIGH for receive state and LOW for transmit state. The polarity of the
RTS# pin can be inverted via EFCR bit-5.
Data Rate
The M1170 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate, 8 Mbps at 3.3V
with 8X sampling clock rate, and 4 Mbps at 3.3V with 16X internal sampling clock rate. The device can operate
with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1
pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for
data rates of up to 3.68 Mbps.
The rich feature set of the M1170 is available through the internal registers. Automatic hardware/software flow
control, programmable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the M1170 is software compatible with previous generation of
UARTs, 16C450, 16C550 and 16C2550.
5
5 Page 
XR20M1170
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
2.5 Crystal Oscillator or External Clock Input
The M1170 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in
each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the
output. Please note that the input XTAL1 is not 5V tolerant and so the maximum at the pin should be VCC. For
programming details, see ““Section 2.6, Programmable Baud Rate Generator with Fractional Divisor” on
page 11.”
FIGURE 11. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120 Ω
R2 (Optional)
500 ΚΩ− 1 ΜΩ
Y1
1.8432 MHz
to
24 MHz
C1
22-47 pF
C2
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 11). The programmable
Baud Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with
an external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (16 Mbps serial data rate) at
3.3V with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note
DAN108 on the EXAR web site at http://www.exar.com.
2.6 Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon power-up. Therefore, the BRG must be
programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part
of the divisor and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are
used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud
Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data rate.
Table 6 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the
pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X
sampling rate, these data rates would double and at 4X sampling rate, these data rates would quadruple. Also,
when using 8X sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an
11
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| PDF Descargar | [ Datasheet XR20M1170.PDF ] | |
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