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PDF XRT94L43 Data sheet ( Hoja de datos )
| Número de pieza | XRT94L43 | |
| Descripción | SONET/SDH OC-12 TO 12XDS3/E3 MAPPER | |
| Fabricantes | Exar Corporation | |
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XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
NOVEMBER 2006
REV. 1.0.2
GENERAL DESCRIPTION
The XRT94L43 is an SDH to PDH physical layer
processor with integrated SONET OC-12 and 12
DS3/E3 framing controller. The XRT94L43 contains
an integral SONET framer which provides framing
and error accumulation in accordance with ANSI/ITU-
T specifications. For a multiple channel DS3/E3
feature, each channel contains identical elements.
The configuration of this device is through internal
registers accessible via an 8-bit parallel, memory
mapped, microprocessor interface.
The SONET/SDH transmit and receive blocks are
used to transmit/receive an STS-12/STM-4 signals or
compose and decompose 12, STS-1/DS3/E3 signals.
The blocks operate at a peak internal clock speed of
77 MHz and support 8-bit internal data paths. The
transmit and receive blocks are compliant with both
SONET and SDH standards.
The XRT94L43 performs all SONET transport and
path overhead processing for use in broadband data
transport applications.
FEATURES
• Single Chip solution for 12 DS3/E3 to SONET/SDH
Mapping
• Generates and terminates SONET section, line and
path layers.
• Provides SONET frame scrambling and
descrambling.
• Differential Line Interfaces
• 8-bit microprocessor interface
• Requires +2.5 and +3.3V power supplies with +5V
input tolerance
• -40°C to +85°C Operating Temperature Range
• Available in a 516 Ball PBGA package
APPLICATIONS
• Network switches
• Concentrators
• Frame Relay Switches
• SONET Customer Premises Multiplexers
• Network Access Equipment
• Test/Monitoring Equipment
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
REV. 1.0.2
• Contains 12 on-chip 64 byte Expected Receive Path Trace Message Buffer, in which the user will load in an
expected Path Trace Message
• Contains 12 on-chip 64 byte Actual" Receive Path Trace Message Buffers, that will contain the actual
Received Path Trace Message
• The SONET Receiver will use the contents within both the Expected and Actual Receive Path Trace
Message Buffers to either declare or clear the TIM-P defect condition
• Computes and verifies the B3 bytes within each incoming STS-1 SPE/VC-3 or STS-3c SPE/VC-4 and
increments on-chip Performance Monitoring registers each time it detects B3 byte errors.
• Detects and Flags Line - Remote Error Indicator (REI-L) and Path - Remote Error Indicator (REI-P) events,
and increments on-chip Performance Monitoring registers each time it detects REI-L or REI-P events
• Computes and verifies both the B1 and B2 bytes within the incoming STS-12/STM-4 data-stream and
increments on-chip Performance Monitoring registers each time it detects B1 or B2 byte errors
MAPPER
• Maps DS3 data into/De-maps DS3 data from an STS-1 SPE per the requirements in Telcordia GR-253-
CORE
• Maps DS3/E3 data into/De-Maps DS3/E3 data from a VC-3 per ITU-T G.707
• Implements AU-3 to VC-3 multiplexing and de-multiplexing
DS3 RECEIVE FRAMER
• Offers off-line framing algorithm
• Complies with the standards as: Bellcore TR-NWT-000499 and TR-NWT-000009
• Supports overhead extraction
• Detects and flags LCV (Line Code Violations) and EXZ (Excessive Zero Events).
• Reports and counts FEBE
• HDLC controller complies with ITU-T Q.921 LAPD protocol
• Provides Line and Local Loop-backs
• Supports either the M13 or the C-bit Parity Framing formats
• Supports B3ZS line decoding which can be user enabled.Replaces valid B0V or 00V with 3 zeros
• Synchronizes to incoming frame based upon 10 valid F bits followed by 3 consecutive valid M frames, Offers
optional AIC-bit or parity verification before declaration of sync
• Detects Out of Frame (OOF) upon 3 or 6 F bits out of 15 F bits in error or 1 or more M bits in 3 of 4
consecutive frames in error
• Detects Loss of Signal (LOS) upon encountering 180 consecutive 0’s and clears on at least 60 of successive
received 1’s.Offers optional disable
• Detects idle state by checking C-bit in subframe 3 are all zero, X-bits are one and repeating 11001100
payloads. Declaration occurs when all the above conditions persist for 63 M-frames. Clears the condition
when 63 valid M-frames are received
• Detects AIS with different algorithm
• Computes and verifies P and CP-Bits
• Validate FERF bits, sets to one when both X-bits are zero and clears when they are One
• Detects and validates FEAC codes upon 8 out of 10 last identical received codes.Invalidates on 3 in 10
mismatch
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5 Page 
XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
TABLE OF CONTENTS
REV. 1.0.2
GENERAL DESCRIPTION ................................................................................................ 1
FEATURES ................................................................................................................................................. 1
APPLICATIONS .......................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SONET MODE ..................................................................... 2
FIGURE 2. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SDH/TUG-3 MODE .............................................................. 3
FIGURE 3. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SDH/AU-3 MODE ................................................................. 3
PRODUCT FEATURES ..................................................................................................... 4
SONET TRANSMITTER .................................................................................................................................. 4
SONET RECEIVER........................................................................................................................................ 4
MAPPER ....................................................................................................................................................... 5
DS3 RECEIVE FRAMER ................................................................................................................................. 5
DS3 TRANSMIT FRAMER ............................................................................................................................... 6
E3 RECEIVE FRAMER .................................................................................................................................... 6
E3 TRANSMIT FRAMER .................................................................................................................................. 7
E3/DS3/STS-1 DE-JITTERING/DE-SYNC CIRCUIT .......................................................................................... 8
PERFORMANCE MONITORING ......................................................................................................................... 8
INTERRUPT, STATUS AND TEST...................................................................................................................... 8
ORDERING INFORMATION............................................................................................................................. 10
FIGURE 4. PIN OUT OF THE XRT94L43.......................................................................................................................................... 10
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS - DIRECT ADDRESSING ............................................................... 8
MICROPROCESSOR INTERFACE ...................................................................................................................... 8
SONET/SDH SERIAL LINE INTERFACE PINS ................................................................................................ 13
STS-12/STM-4 TELECOM BUS INTERFACE - TRANSMIT DIRECTION .............................................................. 19
STS-12/STM-4 TELECOM BUS INTERFACE - RECEIVE DIRECTION ................................................................ 22
SONET/SDH OVERHEAD INTERFACE - TRANSMIT DIRECTION ...................................................................... 24
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION ................................................................ 33
RXSTS-1 TOH/POH INTERFACE................................................................................................................. 82
STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION .................................................................. 85
RECEIVE TRANSPORT OVERHEAD INTERFACE............................................................................................. 128
GENERAL PURPOSE INPUT/OUTPUT ........................................................................................................... 135
CLOCK INPUTS .......................................................................................................................................... 139
BOUNDARY SCAN ...................................................................................................................................... 139
MISCELLANEOUS PINS ............................................................................................................................... 139
POWER SUPPLY PINS................................................................................................................................ 140
VDD = 3.3V ............................................................................................................................................ 140
VDD (2.5V).............................................................................................................................................. 140
GROUND................................................................................................................................................... 142
NO CONNECTS.......................................................................................................................................... 142
PIN DESCRIPTIONS - INDIRECT ADDRESSING ....................................................... 144
MICROPROCESSOR INTERFACE .................................................................................................................. 144
SONET/SDH SERIAL LINE INTERFACE PINS .............................................................................................. 146
STS-12/STM-4 TELECOM BUS INTERFACE - TRANSMIT DIRECTION ............................................................ 153
STS-12/STM-4 TELECOM BUS INTERFACE - RECEIVE DIRECTION .............................................................. 156
SONET/SDH OVERHEAD INTERFACE - TRANSMIT DIRECTION .................................................................... 158
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION .............................................................. 167
RXSTS-1 TOH/POH INTERFACE............................................................................................................... 219
STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION ................................................................ 222
RECEIVE TRANSPORT OVERHEAD INTERFACE............................................................................................. 272
GENERAL PURPOSE INPUT/OUTPUT ........................................................................................................... 279
CLOCK INPUTS .......................................................................................................................................... 287
BOUNDARY SCAN ...................................................................................................................................... 287
MISCELLANEOUS PINS ............................................................................................................................... 287
I
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| PDF Descargar | [ Datasheet XRT94L43.PDF ] | |
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