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PDF XRT94L31 Data sheet ( Hoja de datos )
| Número de pieza | XRT94L31 | |
| Descripción | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
MARCH 2007
REV. 1.0.1
GENERAL DESCRIPTION
The XRT94L31 is a highly integrated SONET/SDH
terminator designed for E3/DS3/STS-1 mapping/de-
mapping functions from either the STS-3 or STM-1
data stream. The XRT94L31 interfaces directly to the
optical transceiver.
The XRT94L31 processes the section, line and path
overhead in the SONET/SDH data stream. The
processing of path overhead bytes within the STS-1s
or TUG-3s includes 64 bytes for storing the J1 bytes.
Path overhead bytes can be accessed through the
microprocessor interface or via serial interface.
The XRT94L31 uses the internal E3/DS3 De-
Synchronizer circuit with an internal pointer leak
algorithm for clock smoothing as well as to remove
the jitter due to mapping and pointer movements.
These De-Synchronizer circuits do not need any
external clock reference for its operation.
The SONET/SDH transmit blocks allow flexible
insertion of TOH and POH bytes through both
Hardware and Software. Individual POH bytes for the
transmitted SONET/SDH signal are mapped either
from the XRT94L31 memory map or from external
interface. A1, A2 framing pattern, C1 byte and H1, H2
pointer byte are generated.
The SONET/SDH receive blocks receive SONET
STS-3 signal or SDH STM-1 signal and perform the
necessary transport and path overhead processing.
The XRT94L31 provides a line side APS (Automatic
Protection Switching) interface by offering redundant
receive serial interface to be switched at the frame
boundary.
The XRT94L31 provides 3 mappers for performing
STS-1/VC-3 to STS-1/DS3/E3 mapping function, one
for each STS-1/DS3/E3 framers.
A PRBS test pattern generation and detection is
implemented to measure the bit-error performance.
A general-purpose microprocessor interface is
included for control, configuration and monitoring.
APPLICATIONS
• Network switches
• Add/Drop Multiplexer
• W-DCS Digital Cross Connect Systems
FEATURES
• Provides DS3/ E3 mapping/de-mapping for up to 3
tributaries through SONET STS-1 or SDH AU-3
and/or TUG-3/AU-4 containers
• Generates and terminates SONET/SDH section,
line and path layers
• Integrated SERDES with Clock Recovery Circuit
• Provides SONET frame scrambling and
descrambling
• Integrated Clock Synthesizer that generates 155
MHz and 77.76 MHz clock from an external 12.96/
19.44/77.76 MHz reference clock
• Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit
that de-jitter gapped clock to meet 0.05UIpp jitter
requirements
• Access to Line or Section DCC
• Level 2 Performance Monitoring for E3 and DS3
• Supports mixing of STS-1E and DS3 or E3 and
DS3 tributaries
• E3 and DS3 framers for both Transmit and Receive
directions
• Complete Transport/Section Overhead Processing
and generation per Telcordia and ITU standards
• Single PHY and Multi-PHY operations supported
• Full line APS support for redundancy applications
• Loopback support for both SONET/SDH as well as
E3/DS3/STS-1
• Boundary scan capability with JTAG IEEE 1149·8-
bit microprocessor interface·
• 3.3 V ± 5% Power Supply; 5 V input signal
tolerance
• -40°C to +85°C Operating Temperature Range
• Available in a 504 Ball TBGA package
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT94L31
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O TYPE
DESCRIPTION
AC18 PRD_L/DS*/WE*
I TTL
READ Strobe /Data Strobe:
The function of this input pin depends upon which mode the Micropro-
cessor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - RD* - READ Strobe Input:
If the Microprocessor Interface is operating in the Intel-Asynchronous
Mode, then this input pin will function as the RD* (Active "Low" READ
Strobe) input signal from the Microprocessor. Once this active-low sig-
nal is asserted, then the XRT94L31 will place the contents of the
addressed register (or buffer location) on the Microprocessor Bi-direc-
tional Data Bus (D[7:0]). When this signal is negated, the Data Bus will
be tri-stated.
Motorola-Asynchronous (68K) Mode - DS* - Data Strobe Input:
If the Microprocessor Interface is operating in the Motorola Asynchro-
nous Mode, then this input will function as the DS* (Data Strobe) input
signal.
PowerPC 403 Mode - WE* - Write Enable Input:
If the Microprocessor Interface is operating in the PowerPC 403 Mode,
then this input pin will function as the WE* (Write Enable) input pin.
Anytime the Microprocessor Interface samples this active-low input sig-
nal (along with CS* and WR*/R/W*) also being asserted (at a logic level)
upon the rising edge of PCLK, then the Microprocessor Interface will
(upon the very same rising edge of PCLK) latch the contents on the Bi-
Directional Data Bus (D[7:0]) into the target on-chip register or buffer
location within the XRT94L31.
AG23
ALE/AS_L
I TTL
Address Latch Enable/Address Strobe:T
he function of this input pin depends upon which mode the Microproces-
sor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - ALE
If the Microprocessor Interface (of the XRT94L31) has been configured
to operate in the Intel-Asynchronous Mode, then this active-high input
pin is used to latch the address (present at the Microprocessor Interface
Address Bus input pins (A[14:0]) into the XRT94L31 Microprocessor
Interface block and to indicate the start of a READ or WRITE cycle. Pull-
ing this input pin "High" enables the input bus drivers for the Address
Bus input pins (A[14:0]). The contents of the Address Bus will be latched
into the XRT94L31 Microprocessor Interface circuitry, upon the falling
edge of this input signal.
Motorola-Asynchronous (68K) Mode - AS*
If the Microprocessor Interface has been configured to operate in the
Motorola-Asynchronous Mode, then this active-low input pin is used to
latch the data (residing on the Address Bus, A[14:0]) into the Micropro-
cessor Interface circuitry of the XRT94L31.
Pulling this input pin "Low" enables the input bus drivers for the Address
Bus input pins. The contents of the Address Bus will be latched into the
Microprocessor Interface circuitry, upon the rising edge of this signal.
PowerPC 403 Mode - No Function - Tie to GND:
If the MIcroprocessor Interface has been configured to operate in the
PowerPC 403 Mode, then this input pin has no role nor function and
should be tied to GND.
5
5 Page 
XRT94L31
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O TYPE
DESCRIPTION
P1 REFTTL I TTL 19.44MHz or 77.76MHz Clock Synthesizer Reference Clock Input
Pin:
The function of this input pin depends upon whether or not the Clock
Synthesizer block is enabled.
If Clock Synthesizer is Enabled.
If the Clock Synthesizer block is enabled, then it will be used to generate
the 155.52MHz, 19.44MHz and/or 77.76MHz clock signal for the Trans-
mit STS-3/STM-1 circuitry. In this mode, the user should apply a clock
signal of any of the following frequencies to this input pin.
• 19.44 MHz
• 38.88 MHz
• 51.84 MHz
• 77.76 MHz
Afterwards, the user needs to write the appropriate data into the Trans-
mit Line Interface Control Register (Address Location = 0x0383) in order
to (1) configure the Clock Synthesizer Block to accept any of the above-
mentioned signals and generate a 155.52MHz, 19.44MHz or 77.76MHz
clock signal, (2) to configure the Clock Synthesizer to function as the
Clock Source for the STS-3/STM-1 block.
If Clock Synthesizer is NOT Enabled:
If the Clock Synthesizer block is NOT enabled, then it will NOT be used
to generate the 19.44MHz and/or 77.76MHz clock signal, for the STS-3/
STM-1 block. In this configuration seting, the user MUST apply a
19.44MHz clock signal to this input pin.
NOTE: The user must place a clock signal to this input pin in order to
perform READ and WRITE operations to much of the SONET/
SDH-related registers via the Microprocessor Interface.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT94L31.PDF ] | |
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