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PDF XRT91L82 Data sheet ( Hoja de datos )
| Número de pieza | XRT91L82 | |
| Descripción | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
APRIL 2005
GENERAL DESCRIPTION
The XRT91L82 is a fully integrated SONET/SDH
transceiver for OC-48/STM16 applications supporting
the use of Forward Error Correction (FEC) capability.
The transceiver includes an on-chip Clock Multiplier
Unit (CMU), which uses a high frequency Phase-
Locked Loop (PLL) to generate the high-speed
transmit serial clock from slower external clock
references. It also provides Clock and Data Recovery
(CDR) functions by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial
data stream. The chip provides serial-to-parallel and
parallel-to-serial converters and 16-bit Differential
LVDS/LVPECL, or Single-Ended LVPECL system
interfaces in both receive and transmit directions.
The transmit section includes a 16x9 Elastic Buffer
(FIFO) to absorb any phase differences between the
transmitter clock input and the internally generated
transmitter reference clock. In the event of an
overflow, an internal FIFO control circuit outputs an
OVERFLOW indication. The FIFO under the control
REV. P1.0.5
of the FIFO_AUTORST register bit can automatically
recover from an overflow condition. The operation of
the device can be monitored by checking the status
of the LOCKDET_CMU and LOCKDET_CDR output
signals. An on-chip phase/frequency detector and
charge-pump offers the ability to form a de-jittering
PLL with an external VCXO that can be used in loop
timing mode to clean up the recovered clock in the
receive section.
APPLICATIONS
• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment
FIGURE 1. BLOCK DIAGRAM OF XRT91L82
OVERFLOW
FIFO_RST
TXDI[15:0]P/N
16
TXPCLKIP/N
TXPCLKOP/N
TXCLKO16P/N
TXCLKO16SEL
STS-48 TRANSCEIVER
WP
RP
RLOOPP
Div by
16
PISO
(Parallel Input
Serial Output)
Re-Timer
CMU
DLOOP RLOOPS
RXDO[15:0]P/N
RXPCLKOP/N
DISRD
DISRDCLK
TDO
TDI
TCK
TMS
TRST
SIPO
(Serial Input
Parallel Output)
16
Div by
16
JTAG
Serial
Microprocessor
Hardware
Control
CDR
TXOP/N
TXSCLKOP/N
RXIP/N
PFD
& Charge Pump
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
REV. P1.0.5
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 26
TABLE 10: CLOCK MULTIPLIER UNIT PERFORMANCE ....................................................................................................................... 26
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 26
TABLE 11: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS ............................................................................................ 27
FIGURE 14. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO (HOST MODE ONLY) .......................................................... 27
3.8 EXTERNAL LOOP FILTER (HOST MODE ONLY) ........................................................................................ 28
FIGURE 15. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER .................................................................................................. 28
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 28
FIGURE 16. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 28
TABLE 12: DIFFERENTIAL CML OUTPUT SWING PARAMETERS......................................................................................................... 28
FIGURE 17. CML DIFFERENTIAL VOLTAGE SWING........................................................................................................................... 29
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 30
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 30
FIGURE 18. SERIAL REMOTE LOOPBACK......................................................................................................................................... 30
4.2 PARALLEL REMOTE LOOPBACK (HOST MODE ONLY) ........................................................................... 30
FIGURE 19. PARALLEL REMOTE LOOPBACK .................................................................................................................................... 30
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 31
FIGURE 20. DIGITAL LOOPBACK...................................................................................................................................................... 31
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 32
4.4.1 JITTER TOLERANCE: ................................................................................................................................................ 32
FIGURE 21. JITTER TOLERANCE MASK............................................................................................................................................ 32
FIGURE 22. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16 ............................ 33
FIGURE 23. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE ..................................... 33
4.4.2 JITTER TRANSFER .................................................................................................................................................... 33
FIGURE 24. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16 .............................. 33
FIGURE 25. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE ....................................... 33
4.4.3 JITTER GENERATION................................................................................................................................................ 34
FIGURE 26. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.488 GBPS .............................. 34
FIGURE 27. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.666 GBPS .............................. 34
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ......................................................................... 35
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 35
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 35
FIGURE 29. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 35
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 36
5.2.1 R/W (SCLK1)............................................................................................................................................................... 36
5.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 36
5.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 36
5.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 36
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 36
6.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 37
TABLE 13: MICROPROCESSOR REGISTER MAP................................................................................................................................ 37
TABLE 14: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................. 38
TABLE 15: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................. 39
TABLE 16: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................. 40
TABLE 17: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................. 41
TABLE 18: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ................................................................................................. 42
TABLE 19: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION ................................................................................................. 43
TABLE 20: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION ................................................................................................. 45
TABLE 21: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION ................................................................................................. 46
TABLE 22: MICROPROCESSOR REGISTER 0X3CH BIT DESCRIPTION................................................................................................. 48
TABLE 23: MICROPROCESSOR REGISTER 0X3DH BIT DESCRIPTION................................................................................................. 49
TABLE 24: MICROPROCESSOR REGISTER 0X3FH BIT DESCRIPTION ................................................................................................. 49
7.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 50
ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 50
ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS ............................................................. 50
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 50
LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS .......................................................... 51
LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS............................................................... 51
LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS ........................................................... 52
ORDERING INFORMATION .................................................................................................................. 53
196 SHRINK THIN BALL GRID ARRAY .............................................................................................. 53
(15.0 MM X 15.0 MM, STBGA).......................................................................................................... 53
II
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REV. P1.0.5
TRANSMITTER SECTION
NAME
LEVEL
TXDI0P
TXDI0N
TXDI1P
TXDI1N
TXDI2P
TXDI2N
TXDI3P
TXDI3N
TXDI4P
TXDI4N
TXDI5P
TXDI5N
TXDI6P
TXDI6N
TXDI7P
TXDI7N
TXDI8P
TXDI8N
TXDI9P
TXDI9N
TXDI10P
TXDI10N
TXDI11P
TXDI11N
TXDI12P
TXDI12N
TXDI13P
TXDI13N
TXDI14P
TXDI14N
TXDI15P
TXDI15N
LVDS,
LVPECL
Diff and SE
TXOP
TXON
CMLDIFF
TXSWING
/ INT
LVTTL,
LVCMOS
TYPE
I
O
I/O
PRELIMINARY
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PIN
P14
P13
N10
N9
N13
N12
M11
M10
M14
M13
L10
L9
L13
L12
K12
K11
J14
K14
J10
K10
J13
J12
H9
J9
H12
H11
G11
G10
F12
G12
G8
G7
A6
A5
D10
DESCRIPTION
Transmit Parallel Data Input
The 155.52 Mbps 16-bit parallel transmit data input should be
applied to the transmit parallel bus simultaneously to be sam-
pled at the rising edge of the TXPCLKIP/N input. The 16-bit
parallel interface is multiplexed into the transmit serial output
interface, MSB first (TXDI15P/N). TXDI[15:0]P/N 100 Ω internal
termination is controlled by INTERM pin or register bit. Inputs
are internally biased to VDD_IO - 1V for AC coupled applica-
tions. For LVPECL Single-Ended applications, either a 100K
VBB bias reference must be provided or the SE_REF pin can
also be used to bias and connected all the negative polarity "N"
pins.
NOTE: The XRT91L82 can accept 166.63 Mbps 16-bit parallel
transmit data input for Forward Error Correction (FEC)
Applications.
Transmit Serial Data Output
The transmit serial data output stream is generated by multi-
plexing the 16-bit parallel transmit data input into a 2.488 Gbps
serial data output stream. In Forward Error Correction, the
transmit serial data output stream is 2.666 Gbps.
Transmit Serial CML Output Swing Mode
Hardware Mode Selects the generated transmit serial CML
Output swing to the optical module.
"Low" = Low Swing CML Mode
"High" = High Swing CML Mode
This pin is provided with an internal pull-up.
Host Mode This pin is functions as the microprocessor Inter-
rupt Output.
NOTE: This pin becomes an open drain output in Host Mode
and requires an external pull-up resistor.
8
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT91L82.PDF ] | |
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