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PDF W311 Data sheet ( Hoja de datos )

Número de pieza W311
Descripción FTG
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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1W311
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W311
FTG for VIA Pro-266 DDR Chipset
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for VIA Pro-2000
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog Timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when Watchdog Timer
time-out
• Capable of generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for CPU and PCI output
clocks
• Programmable output skew between CPU, AGP and PCI
• Supports Intel® Celeron® and Pentium® III class pro-
cessor
• Three copies of CPU output
• Nine copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• Three copies of APIC output
• Supports frequencies up to 200 MHz
• SMBus interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU Cycle-to-Cycle Jitter:...........................................250 ps
CPU to CPU Output Skew:..........................................175 ps
PCI Cycle to Cycle Jitter:.............................................500 ps
PCI to PCI Output Skew: .............................................500 ps
Block Diagram
X1
X2
CPU_STOP#
PWR_DWN#
FS0:1
X TA L
OSC
DIV
PLL Ref Freq
DIV
PLL 1
Stop
Clock
Control
÷6, ÷8,
÷10, ÷12
PCI_STOP#
SD ATA
SCLK
SMBus
Logic
Stop
Clock
Control
VDD_REF
REF0
R E F 1 /F S 4
V D D _ A P IC
A P IC 0 :1
VDD_AGP
A G P 0:2
VDD_CPU
C P U 1 :3
VDD_PCI
P C I_ F
P C I1 :8
RST#
VDD_48 MHz
Pin Configuration[1]
VDD_REF
GND_REF
X1
X2
VDD_48 MHz
FS3*/48 MHz
FS2*/24_48 MHz
GND_48 MHz
PCI_F
PCI1
PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
*FS1
*FS0
AGP0
VDD_AGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF0
47 REF1/FS4*
46 VDD_APIC
45 APIC0
44 APIC1
43 GND_APIC
42 APIC2
41 VDD_CPU
40 GND_CPU
39 CPU1
38 CPU2
37 VDD_CPU
36 GND_CPU
35 CPU3
34 CPU_STOP#*
33 PCI_STOP#*
32 RST#
31 VDD_CORE
30 GND_CORE
29 SDATA
28 SCLK
27 AGP2
26 AGP1
25 GND_AGP
PLL2
4 8 M H z/F S 3
÷2
Note:
1. Signals marked with ‘*’ have internal pull-up resistors.
2 4 _ 4 8 M H z/F S 2
Intel, Pentium, and Celeron are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 3, 2003

1 page




W311 pdf
W311
W311 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register 0
Bit
Pin#
Name
Bit 7
- Reserved
Bit 6
- SEL2
Bit 5
- SEL1
Bit 4
- SEL0
Bit 3
- FS_Override
Bit 2
Bit 1
Bit 0
- SEL4
- SEL3
- Reserved
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization.
Default
0
0
0
0
0
1
0
0
Description
Reserved
See Table 5
See Table 5
See Table 5
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
See Table 5
See Table 5
Reserved
Byte 1: Control Register 1
Bit Pin#
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 2
Bit 1
Bit 0
35
38
39
42
Name
Reserved
Spread Select2
Spread Select1
Spread Select0
CPU3
CPU2
CPU1
APIC2
Default
0
0
0
0
1
1
1
1
Description
Reserved
‘000’ = Normal (spread off)
‘001’ = Test Mode
‘010’ = Reserved
‘011’ = Three-Stated
‘100’ = –0.5%
‘101’ = ± 0.5%
‘110’ = ± 0.25%
‘111’ = ± 0.38%
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register 2
Bit Pin#
Bit 7
20
Bit 6
18
Bit 5
17
Bit 4
16
Bit 3
14
Bit 2
13
Bit 1
11
Name
PCI8
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
Default
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
5

5 Page





W311 arduino
W311
Byte 14: Programmable Frequency Select M-Value Register
Bit
Name
Default
Description
Bit 7
Pro_Freq_EN
0 Programmable output frequencies enabled
0 = disabled
1 = enabled
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
0 If Prog_Freq_EN is set, W311 will use the values programmed in
0
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output fre-
quency. The new frequency will start to load whenever CPU_FSELM[6:0] is
0 updated.
0
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same fre-
0 quency ratio stated in the Latched FS[4:0] register. When it is set, W311 will
0
use the frequency ratio stated in the SEL[4:0] register.
W311 supports programmable CPU frequency ranging from 50MHz to
0 248MHz.
Byte 15: Reserved Register
Bit Pin#
Bit 7
47
Bit 6
6
Bit 5
7
Bit 4
21
Bit 3
22
Bit 2
-
Bit 1
-
Bit 0
-
Name
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
Vendor test mode
Vendor test mode
Vendor test mode
Default
X
X
X
X
X
0
1
1
Description
Latched FS[4:0] inputs. These bits are read only.
Reserved. Write with ‘0’.
Reserved. Write with ‘1’
Reserved. Write with ‘1’
Byte 16: Reserved Register
Bit 7
Bit 6
Bit 5
Bit
Pin#
-
-
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
Name
Vendor test mode
Vendor test mode
Vendor test mode
Vendor test mode
Vendor test mode
Vendor test mode
Vendor test mode
Vendor test mode
Default
0
0
0
0
0
0
0
0
Description
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Byte 17: Reserved Register
Bit 7
Bit 6
Bit
Pin#
-
-
Bit 5
Bit 4
Bit 3
-
-
-
Name
Vendor test mode
Vendor test mode
Vendor test mode
Vendor test mode
Vendor test mode
Default
0
0
0
0
0
Description
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
11

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