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PDF XRK69774 Data sheet ( Hoja de datos )
| Número de pieza | XRK69774 | |
| Descripción | 1:14 LVCMOS PLL CLOCK GENERATOR | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
APRIL 2006
REV. P1.0.1
GENERAL DESCRIPTION
The XRK69774 is a PLL based LVCMOS Clock Generator
targeted for high performance and low skew clock distribu-
tion applications. The XRK69774 can select between one
of two reference inputs and provides 15 LVCMOS outputs -
14 outputs (2 banks of 5 and 1 bank of 4) for clock distribu-
tion and 1 for feedback.
The XRK69774 has two LVCMOS inputs to support clock
redundancy. Switching the internal reference clock is con-
trolled by the control input, CLK_SEL.
The XRK69774 uses PLL technology to frequency lock its
outputs to the input reference clock. The divider in the feed-
back path will determine the frequency of the VCO. Each of
the separate output banks can individually divide down the
VCO output frequency. This allows the XRK69774 to gen-
erate a multitude of different bank frequency ratios and out-
put-to-input frequency ratios.
The outputs of the XRK69774 can be immobilized, in the
low state, by use of the stop clock feature. Global output
disabling and reset can be achieved with the control input
MR/OE.
The XRK69774 has an output frequency range of 8.33MHz
FIGURE 1. BLOCK DIAGRAM OF THE XRK69774
to125MHz and an input frequency range of 4.16MHz to
62.5MHz.
FEATURES
• Fully Integrated PLL
• 15 LVCMOS outputs
■ 2 banks with 5 outputs and 1 with 4 outputs
each
■ 1 dedicated feedback for frequency control
■ Output Frequency of each Bank can be
individually controlled
• VCO Range 200MHz to 500MHz
• Output freq. range: 8.33MHz to 125MHz
• Max Output Skew of 175ps
• Max Cycle-to-cycle jitter: 90ps
• LVCMOS inputs for reference clock source
APPLICATIONS
• System Clock generator
• Zero Delay Buffer
VDD
CLK0
CLK1
CLK_SEL
FB_IN
PLL_EN
VCO_SEL
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
0
1
VDD
0
Ref VCO 1
PLL
200-500MHz
FB
÷2 0
÷4 1
2
VDD
__________
STOP_CLK
VDD
___
MR/OE
POR
Divider Select
÷2, ÷4
÷2, ÷4
÷4, ÷6
÷4, ÷6, ÷8, ÷12
STOP
CLK
STOP
CLK
STOP
CLK
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
QC0
QC1
QC2
QC3
QFB
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. P1.0.1
PRELIMINARY
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
TABLE 4: AC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
CONDITION
fREF Input reference frequency
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
fVCO
fMAX
VCO frequency range
Output frequency
tPW
ItR, ItF
t(∅)
tSK(O)
CLKx pulse width
Input CLKx Rise/Fall time
Propagation Delay (static
phase offset)a
Output to output skew
DC Output duty cycle
OtR, OtF Output Rise/Fall time
tPLZ, tPHZ Output Disable Time
tPZL, tPZH Output Enable Time
tJIT(CC) Cycle-to-Cycle Jitter Time
tJIT(PER) Period Jitter
tJIT(∅)
I/O Phase Jitter (rms)
VCO= 400MHz
PLL bypass mode
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
0.8V to 2.0V
CLK to FB_IN
fREF = 50MHz & FB = ÷8
Bank A (QAx to QAy)
Bank B (QBx to QBy)
Bank C (QCx to QCy)
all outputs (QXy to QWz)
0.55 to 2.4V
All outputs @ same
frequency
All outputs @ same
frequency
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
NOTE:
a. t(∅) = +50ps ± (1÷ (120 x fREF)) for any reference frequency.
MIN
25.0
16.6
12.5
8.33
6.25
4.16
200
50.0
25.0
16.6
12.5
8.33
2.0
-250
47
0.1
TYP
MAX
UNIT
62.5
41.6
31.25
20.83
15.625
10.41
MHz
MHz
MHz
MHz
MHz
MHz
250
500
125
62.5
41.6
31.25
20.83
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
+100
100
125
100
175
50 53
1.0
10
10
90
90
15
49
18
22
26
34
ps
ps
ps
ps
ps
%
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
5
5 Page 
REV. P1.0.1
PRELIMINARY
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.0
April 7, 2006 Initial release
P1.0.1
April 10, 2006 General Description edit last line to: ...input frequency range of 4.16MHz to 62.5MHz.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet April 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
11
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