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PDF XRK4991A Data sheet ( Hoja de datos )
| Número de pieza | XRK4991A | |
| Descripción | SKEW CLOCK BUFFER | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
FEBRUARY 2005
FUNCTIONAL DESCRIPTION
The XRK4991A 3.3V High-Speed Low-Voltage
Programmable Skew Clock Buffer offers user
selectable control over system clock functions to
optimize the timing of high-performance computer
systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified
output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or
function configurations. Delay increments of 0.7 to
1.5 ns are determined by the operating frequency
with outputs able to skew up to ±6 time units from
their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission
line delay effects to be canceled. When this “zero
delay” capability is combined with the selectable
output skew functions, the user can create output-to-
output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are
provided for additional flexibility in designing complex
clock systems. When combined with the internal PLL,
these divide functions allow distribution of a low-
frequency clock that can be multiplied by two or four
REV. P1.0.2
at the clock destination. This feature minimizes clock
distribution difficulty while allowing maximum system
clock speed and flexibility.
FEATURES
• Ref input is 5V tolerant
• 3 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge
synchronization: Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 85MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 2 skew grades
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• 32-pin PLCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
• Green packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK4991A
TEST
PE
FB_IN
CLKIN
PHASE
FREQ
DET
FSEL
FILTER
SELD0
SELD1
SELC0
Select Inputs
SELC1
SELB0
SELB1
SELA0
SELA1
VCO AND TIME
UNIT GENERATOR
SKEW
SELECT
MATRIX
0E
QD0
QD1
QC0
QC1
QB0
QB1
QA0
QA1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
REV. P1.0.2
FSEL[2,3]
LOW
MID
HIGH
PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
TABLE 2: FREQUENCY RANGE SELECT AND tU CALCULATION [1]
fNOM (MHZ)
tU = 1 / fNOM X N
MIN
MAX
WHERE N =
15 30 44
25 50 26
40 85 16
APPROXIMATE
FREQUENCY (MHZ) AT
WHICH tU = 1.0ns
22.7
38.5
62.5
SKEW SELECT MATRIX
The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout
drivers (Qx[0:1]), and two corresponding three-level function select (SELx[0:1]) inputs. Table 2 below shows
the nine possible output functions for each section as determined by the function select inputs. All times are
measured with respect to the CLKIN input assuming that the output connected to the FB_IN input has 0tU
selected.
TABLE 3: PROGRAMMABLE SKEW CONFIGURATIONS [1]
FUNCTION SELECTS
OUTPUT FUNCTIONS
SELX1
SELX0
QA[1:0], QB[1:0]
QC[1:0]
QD[1:0]
LOW
LOW
-4tU
Divide by 2
Divide by 2
LOW
MID
-3tU
-6tU
-6tU
LOW
HIGH
-2tU
-4tU
-4tU
MID LOW -1tU -2tU -2tU
MID MID
0tU
0tU
0tU
MID HIGH +1tU
+2tU
+2tU
HIGH
LOW
+2tU
+4tU
+4tU
HIGH
MID
+3tU
+6tU
+6tU
HIGH
HIGH
+4tU
Divide by 4
Inverted
NOTES:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID
indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2.
2. The level to be set on FSEL is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit
Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at QA0 and the other outputs
when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN
inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN
inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output
as the FB_IN input.
3. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached
2.8V.
5
5 Page 
xr
REV. P1.0.2
PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
FIGURE 5. AC TIMING DIAGRAM
CLKIN
FB_IN
tREF
tRPWH
tPD
tRPWL
tODCV
tODCV
Any Q
OTHER Q
tSKEWPR,
tSKEW0, 1
INVERTED Q
CLKIN DIVIDED BY 2
CLKIN DIVIDED BY 4
tSKEW3, 4
tSKEW1, 3, 4
tSKEWPR,
tSKEW0, 1
tSKEW2
tSKEW3, 4
tJR
tSKEW2
tSKEW3, 4
tSKEW2, 4
NOTES:
1. PE: The AC Timing Diagram applies to PE=VCC. For PE=GND, the negative edge of FB_IN aligns with the
negative edge of CLKIN, divided outputs change on the negative edge of CLKIN, and the positive edges of the
divide-by-2 and the divide-by-4 signals align.
2. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay
has been selected when all are loaded with 20pF and terminated with 75Ω to VCC/2.
3. tSKEWPR: The skew between a pair of outputs (Qx[1:0]) when all eight outputs are selected for 0tU.
4. tSKEW0: The skew between outputs when they are selected for 0tU.
5. tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient
temperature, air flow, etc.)
6. tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and
tSKEW4 specifications.
7. tPWH is measured at 2V.
8. tPWL is measured at 0.8V.
9. tORISE and tOFALL are measured between 0.8V and 2V.
10. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at CLKIN or FB_IN until tPD is within specified limits.
11
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| PDF Descargar | [ Datasheet XRK4991A.PDF ] | |
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