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PDF XRK39653 Data sheet ( Hoja de datos )
| Número de pieza | XRK39653 | |
| Descripción | 8-OUTPUT ZERO DELAY BUFFER | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
FEBRUARY 2006
XRK39653 GENERAL DESCRIPTION
The XRK39653 is a low voltage high performance PLL
based zero delay buffer/clock generator designed for high
speed clock distribution applications. It provides 9 low
skew, low jitter outputs ideal for networking, computing and
telecom applications.
The PLL based design allows the 9 outputs (8 clock outputs
and 1 feedback output) to be phase aligned to the input ref-
erence clock. The outputs source LVCMOS compatible lev-
els and can drive 50Ω transmission lines. If series
termination is used, each output can drive up to 2 lines pro-
viding effectively a fanout of 1:16. The XRK39653’s refer-
ence input accepts a LVPECL clock source.
For normal operation (PLL used to source the outputs), the
feedback output (QFB) is connected to the feedback input
(FB_IN). The VCO range of operation is 200 to 500MHz.
This means that the input/output ranges are determined by
the divider setting. If ÷4 is used, the input/output range is 50
to 125MHz (high range), if ÷8 is used the input/output range
is 25 to 62.5MHz (low range).
For testing purposes two PLL bypass modes are provided.
The first simply replaces the PLL output with the reference
clock (PLL_EN=0, BYPASS=1). The dividers are still in
REV. P1.0.0
use. The second is a full bypass mode that has the PLL
and divider operation removed (BYPASS=0). In this mode
the reference clock directly sources the outputs drivers.
FEATURES
• 8 LVCMOS Clock Outputs
• 1 Feedback Output
• LVPECL reference clock input
• 25-200 MHz input/output frequency range
■ Input/Output range (÷4): 50-125MHz
■ Input/Output range (÷8): 25-62.5MHz
• 150ps max output to output skew
• Two bypass test mode options
• Fully Integrated PLL
• 3.3V Operation
• Pin compatible with MPC9353
• Industrial temp range: -40°C to +85°C
• 32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK39653
VDD
PECL
PECL
FB_IN
VDD
PLL_EN
VCO_SEL
BYPASS
OE
Ref
PLL
FB
00
0
1 ÷4 1
÷2 1
QFB
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
REV. P1.0.0
PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
AC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) a
SYMBOL
PARAMETER
MIN TYP
MAX
UNIT
CONDITION
tJIT(PER) Period Jitter
100 ps
tJIT(I/O) I/O Phase Jitter (RMS)
25 ps
BW PLL bandwidth
÷4 feedback
÷8 feedback
0.8 - 4
0.5 - 1.3
MHz
MHz
DC Output duty cycle
45 50
55 % PLL locked
tLOCK Maximum PLL Lock Time
10.0 ms
tor/tof Output Rise/Fall time
100
1000
ps 0.55 to 2.4V
tPLZ,HZ Output Disable Time
7 ns
tPHZ,LZ Output Enable Time
6 ns
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
MAXIMUM RATINGSa
SYMBOL
CHARACTERISTICS
VDD Supply Voltage
VIN DC Input Voltage
VOUT DC Output Voltage
IIN DC Input Current
IOUT DC Output Current
TS Storage Temperature
MIN
MAX
UNIT
-0.3 3.9
V
-0.3 VDD+0.3
V
-0.3 VDD+0.3
V
+20 mA
+50 mA
-65 125 °C
CONDITION
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
GENERAL SPECIFICATIONS
SYMBOL
CHARACTERISTICS
VTT Output termination voltage
MM ESD Protection (Machine model)
HBM ESD Protection (Human body model)
LU Latch-up immunity
CIN Input Capacitance
MIN
200
2000
200
TYP
VCC÷2
4.0
MAX
UNIT
V
V
V
mA
pF
CONDITION
Inputs
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet XRK39653.PDF ] | |
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