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PDF XRK39351 Data sheet ( Hoja de datos )
| Número de pieza | XRK39351 | |
| Descripción | 9-OUTPUT PLL CLOCK DRIVER | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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PRELIMINARY
XRK39351
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
FEBRUARY 2006
GENERAL DESCRIPTION
The XRK39351 is a low voltage PLL based clock
driver designed for high speed clock distribution
applications.
The XRK39351 has two reference clock inputs, one
LVPECL and the other LVCMOS. The REF_SEL
input selects clock input to be used as the PLL’s
reference source.
The XRK39351 uses PLL technology to frequency
lock its outputs to the clock reference input. The
divider in the feedback path will determine the
frequency of the VCO. The XRK39351 provides 9
LVCMOS outputs that are separated into 4 banks.
Each of the separate output banks can individually
divide down the VCO output frequency. This allows
the XRK39351 to generate a variety of output-to-input
frequency ratios (1:1, 1:2, 1:4, 2:1 and 4:1). All
outputs provide LVCMOS compatible levels while
driving 50Ω terminated transmission lines.
The input reference clock can be directly applied to
the output dividers bypassing the PLL when PLL_EN
REV. P1.0.0
input is pulled low. This is a test mode intended for
system debug purposes.
The XRK39351 has an output/input frequency range
of 25MHz to 200MHz with the PLL enabled and an
input frequency range of 2MHz to 300MHz when the
PLL is disabled (test mode).
FEATURES
• 9 LVCMOS Outputs (4 banks)
• 25 - 200 MHz output frequency range
• Fully Integrated PLL
• 2.5V or 3.3V Operation
• Selectable reference clock input, LVCMOS or
LVPECL
• 150ps max output to output skew
• Pin compatible with MPC9351
• Industrial temp range: -40°C to +85°C
• 32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK39351
REF_SEL
TCLK
PECL
PECL
FB_IN
PLL_EN
SELA
SELB
SELC
SELD
1
0
VDD
Ref
PLL
FB
0
1
OE
÷2 0
1
÷4
0
÷8
1
0
1
0
1
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
REV. P1.0.0
PRELIMINARY
XRK39351
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
.
AC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) a
SYMBOL
PARAMETER
fVCO VCO Frequency
fref Input Reference Frequency
÷2 feedback
÷4 feedback
÷8 feedback
PLL Bypass
fMAX Max Output Frequency
÷2 feedback
÷4 feedback
÷8 feedback
tir/tif Input Rise/Fall time
frefDC Input Clock duty cycle
tpd Propagation Delay - (SPO, Input clock to FB)
TCLK to FB_IN
PECL to FB_IN
tskew Output-to-Output Skew
tJIT(CC) Cycle-to-Cycle Jitter (RMS)
÷4 feedback
MIN
200
100
50
25
2
100
50
25
25
-50
-25
TYP
10
MAX
400
200
100
50
300
200
100
50
1.0
75
150
325
150
22
tJIT(PER) Period Jitter (RMS)
÷4 feedback
8 15
tJIT(I/O)
BW
I/O Phase Jitter (RMS)
PLL bandwidth
DC Output duty cycle
tLOCK Maximum PLL Lock Time
tor/tof Output Rise/Fall time
tPLZ,HZ Output Disable Time
tPHZ,LZ Output Enable Time
÷2 feedback
÷4 feedback
÷8 feedback
÷2 feedback
÷4 feedback
÷8 feedback
45
47.5
48.75
4 - 17
9.0-20.0
3.0-9.5
1.2-2.1
50
50
50
100
55
52.5
51.75
1.0
1000
10
10
UNIT
MHz
MHz
MHz
CONDITION
PLL_EN = 1
PLL_EN = 1
PLL_EN = 1
PLL_EN = 0
ns 0.8 to 2.0V
%
ps PLL Locked
ps PLL Locked
ps
ps All outputs set
to ÷4
ps All outputs set
to ÷4
ps
MHz
MHz
MHz
%
%
%
ms
100 - 200MHz
50 - 100MHz
25 - 50MHz
ps 0.55 to 2.4V
ns
ns
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet XRK39351.PDF ] | |
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