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PDF XRK32309 Data sheet ( Hoja de datos )

Número de pieza XRK32309
Descripción LOW-COST 3.3V ZERO DELAY BUFFER
Fabricantes Exar Corporation 
Logotipo Exar Corporation Logotipo



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No Preview Available ! XRK32309 Hoja de datos, Descripción, Manual

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PRELIMINARY
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
MAY 2006
REV. P1.0.1
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Offered in both 16 pin SOIC and TSSOP packages,
XRK32309 is a low cost 3.3V zero delay buffer. It is
designed to distribute high speed clocks by taking
one reference input and driving nine output clocks.
The feedback of its on-chip PLL is internally
connected to the FB output. XRK32309 devices
operate over 10-100 MHz frequency range with 30 pF
loads and up to 120MHz with lower loads (10 pF).
The -1H version has higher drive strength than the
base -1 version, featuring faster rise and fall time.
The XRK32309 has two banks each with four
outputs. These outputs are controlled by two select
input lines according to the Table 2, “Select Input
Decoding,” on page 3. In cases where not all outputs
are needed, bank B can be tri-stated. The select
lines also enable putting the device in a bypass mode
where the input is directly applied to the outputs. This
feature is useful for chip and testing purposes.
Some applications may require distributing the clock
to several destinations. In such situations, multiple
XRK32309 devices can be connected to accept the
same input clock and generate several clock signals.
In this case, the skew between the outputs of two
devices is guaranteed to be less than 700 ps.
The available versions of XRK32309 are shown in
Table 12, “Ordering Information,” on page 10. The
XRK32309-1 is the base part.
FEATURES
10-MHz to 120-MHz operating range, compatible
with CPU and PCI bus frequencies
Zero input-output propagation delay
Multiple low-skew outputs
Output-output skew less than 250 ps
Device-device skew less than 700 ps
One input drives nine outputs, grouped as 4 +
4+1
Less than 200 ps cycle-cycle jitter, compatible with
Pentium®-based systems
Test Mode to bypass phase-locked loop (PLL) (see
“Select Input Decoding” on page 2)
Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages
3.3V operation
Industrial and commercial temperature available
FIGURE 1. BLOCK DIAGRAM OF THE XRK32309
REF
PLL MUX
S2 Select Input
Decoding
S1
FB
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRK32309 pdf
REV. P1.0.1
PRELIMINARY
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
TABLE 6: SWITCHING CHARACTERISTICS FOR XRK32309SC-1 COMMERCIAL TEMPERATURE DEVICES[7]
PARAMETER
NAME
TEST CONDITIONS
t1 Output Frequency
30-pF load
10-pF load
DC Duty Cycle[6] = t2 ÷ t1 Measured at 1.4V, FOUT=66.67MHz
t3 Rise Time[6]
Measured between 0.8V and 2.0V
t4 Fall Time[6]
Measured between 0.8V and 2.0V
t5 Output to Output Skew[6] All outputs equally loaded
t6A Delay, REF Rising Edge to Measured at VDD/2
FB Rising Edge[6]
t6B Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
FB Rising Edge[6]
Bypass Mode
t7 Device to Device Skew[6] Measured at VDD/2 on the FB pins of
devices
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67MHz, loaded outputs
tLOCK
PLL Lock Time[6]
Stable power suppy, valid clock
presented on REF pin
MIN
10
10
40.0
-
-
-
-
1
-
-
-
TYP
-
50.0
MAX
100
120
60.0
UNIT
MHz
MHz
%
- 2.50 ns
- 2.50 ns
- 250 ps
0 ±350 ps
5 8.7 ns
0 700 ps
- 200 ps
- 1.0 ms
NOTES:
5. REF input has a threshold voltage of VDD/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
7. All parameters specified with loaded outputs.
5

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XRK32309 arduino
PRELIMINARY
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
PACKAGE DRAWINGS AND DIMENSIONS
FIGURE 6. XRK32309 PACKAGE DRAWING - 16 LEAD SMALL OUTLINE
16 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
D
16
1
Seating
Plane
e
9
EH
8
C
B A1
A
α
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL MIN
MAX MIN MAX
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.386
0.394
9.80
10.00
E
0.150
0.157
3.80
4.00
e 0.050 BSC
1.27 BSC
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
α 0° 8° 0° 8°
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