DataSheet.es    


PDF XRT83VSH38 Data sheet ( Hoja de datos )

Número de pieza XRT83VSH38
Descripción 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
Fabricantes Exar Corporation 
Logotipo Exar Corporation Logotipo



Hay una vista previa y un enlace de descarga de XRT83VSH38 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! XRT83VSH38 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
XRT83VSH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
MARCH 2007
REV. 1.0.7
GENERAL DESCRIPTION
The XRT83VSH38 is a fully integrated 8-channel
short-haul line interface unit (LIU) that operates from
a 1.8V and a 3.3V power supply. Using internal
termination, the LIU provides one bill of materials to
operate in T1, E1, or J1 mode with minimum external
components. The LIU features are programmed
through a standard parallel or serial microprocessor
interface. EXAR’s LIU has patented high impedance
circuits that allow the transmitter outputs and receiver
inputs to be high impedance when experiencing a
power failure or when the LIU is powered off. Key
design features within the LIU optimize 1:1 or 1+1
redundancy and non-intrusive monitoring applications
to ensure reliability without using relays.
The on-chip clock synthesizer generates T1/E1/J1
clock rates from a selectable external clock frequency
and outputs a clock reference of the line rate chosen.
Additional features include RLOS, a 16-bit LCV
counter for each channel, AIS, QRSS generation/
detection, TAOS, DMO, and diagnostic loopback
modes.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH38 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE-AS
CS
RDY_DTACK/SDO
INT
SER_PAR
MASTER CLOCK SYNTHESIZER
1 of 8 channels, CHANNEL_n
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TAOS
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
DRIVE
MONITOR
LINE
DRIVER
QRSS
DETECTOR
Remote
Loopback
Digital
Loopback
Analog
Loopback
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LOS
DETECTOR
AIS
DETECTOR
PEAK
DETECTOR
& SLICER
TEST
MICROPROCESSOR/SERIAL INTERFACE CONTROLLER
MCLKOUT
DMO_n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
ICT
µPTS1
µPTS2
D[7:0]
µPCLK/SCLK
A[7:0]/SDI
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT83VSH38 pdf
REV. 1.0.7
XRT83VSH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
APPLICATIONS ............................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH38 T1/E1/J1 LIU (HOST MODE) .................................................................................... 1
FIGURE 2. BLOCK DIAGRAM OF THE XRT83VSH38 T1/E1/J1 LIU (HARDWARE MODE) ........................................................................... 2
FEATURES..................................................................................................................................................................... 3
ORDERING INFORMATION .................................................................................................................... 3
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTION BY FUNCTION................................................................................................ 5
RECEIVE SECTION ......................................................................................................................................................... 5
TRANSMIT SECTION ....................................................................................................................................................... 7
PARALLEL MICROPROCESSOR INTERFACE ...................................................................................................................... 9
JITTER ATTENUATOR.................................................................................................................................................... 11
CLOCK SYNTHESIZER .................................................................................................................................................. 11
ALARM FUNCTIONS/REDUNDANCY SUPPORT................................................................................................................. 13
SERIAL MICROPROCESSOR INTERFACE......................................................................................................................... 15
POWER AND GROUND.................................................................................................................................................. 15
FUNCTIONAL DESCRIPTION ...................................................................................................... 18
1.0 HARDWARE MODE VS HOST MODE ................................................................................................ 18
1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 18
TABLE 1: DIFFERENCES BETWEEN HARDWARE MODE AND HOST MODE................................................................................................. 18
2.0 MASTER CLOCK GENERATOR ......................................................................................................... 19
FIGURE 3. TWO INPUT CLOCK SOURCE................................................................................................................................................. 19
FIGURE 4. ONE INPUT CLOCK SOURCE ................................................................................................................................................. 19
TABLE 2: MASTER CLOCK GENERATOR ................................................................................................................................................. 19
3.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 20
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 20
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 20
3.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 20
TABLE 3: SELECTING THE INTERNAL IMPEDANCE ................................................................................................................................... 20
FIGURE 6. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 20
3.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 21
TABLE 4: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 21
FIGURE 7. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR ............................................................................. 21
3.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22
FIGURE 8. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 22
FIGURE 9. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................... 22
TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG ................................................................................................................ 22
3.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 22
FIGURE 10. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ............................................................................................ 23
3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 23
FIGURE 11. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN......................................................................................... 23
3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 23
3.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24
3.4 HDB3/B8ZS DECODER .................................................................................................................................. 25
3.5 RPOS/RNEG/RCLK ........................................................................................................................................ 25
FIGURE 12. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 25
FIGURE 13. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 25
3.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 26
FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION................................................................................................... 26
4.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 27
FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 27
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 27
FIGURE 16. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK...................................................................................................... 27
FIGURE 17. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK........................................................................................................ 27
TABLE 6: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 28
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 28
TABLE 7: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 28
TABLE 8: EXAMPLES OF B8ZS ENCODING............................................................................................................................................. 28
4.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 29
I

5 Page





XRT83VSH38 arduino
REV. 1.0.7
SIGNAL NAME
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TAOS0
TAOS1
TAOS2
TAOS3
TAOS4
TAOS5
TAOS6
TAOS7
TXON0
TXON1
TXON2
TXON3
TXON4
TXON5
TXON6
TXON7
BGA
LEAD #
B4
A3
A15
C14
T3
T5
V16
U15
D6
B6
A5
C6
T6
U6
V6
R6
A13
D12
C12
B12
V13
U13
R12
R13
XRT83VSH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TYPE
DESCRIPTION
I Transmit Clock Input
TCLK is the input facility clock used to sample the incoming TPOS/TNEG data. If
TCLK is absent, pulled "Low", or pulled "High", the transmitter outputs at TTIP/
TRING sends an all zero signal to the line. TPOS/TNEG data can be sampled on
either edge of TCLK selected by TCLKE.
NOTE: 1. TCLKE is a global setting that applies to all 8 channels.
NOTE: 2. Internally pulled "Low" with a 50kresistor.
I Transmit All Ones for Channel
Hardware Mode Only
Setting this pin “High” enables the transmission of an all ones pattern to the line
from TTIP/TRING. If this pin is pulled “Low”, the transmitters operate in normal
throughput mode.
NOTE: Internally pulled “Low” with a 50kresistor for all channels. This feature is
available in Host mode by programming the appropriate channel register.
I Transmit On/Off Input
Upon power up, the transmitters are powered off. Turning the transmitters On or
Off is selected through the microprocessor interface by software control while in
Host mode. However, if TxONCNTL is set "High" in software, or if in Hardware
mode, the activity of the transmitter outputs is controlled by the TxON pins.
NOTE: TxON is ideal for redundancy applications. See the Redundancy
Applications Section of this datasheet for more details. Internally pulled
"Low" with a 50Kresistor.
8

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet XRT83VSH38.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
XRT83VSH31414-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNITExar Corporation
Exar Corporation
XRT83VSH31616-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNITExar Corporation
Exar Corporation
XRT83VSH388-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNITExar Corporation
Exar Corporation

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar