PDF XRT83VSH314 Data sheet ( Hoja de datos )

Número de pieza	XRT83VSH314
Descripción	14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
Fabricantes	Exar Corporation
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No Preview Available ! www.DataSheet4U.com XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT SEPTEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT83VSH314 is a fully integrated 14-channel short-haul line interface unit (LIU) that operates from a 1.8V Inner Core and 3.3V I/O power supplies. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per channel basis with minimum external components. The LIU features are programmed through a standard microprocessor interface. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency and has five output clock references that can be used for external timing (8kHz, 1.544Mhz, 2.048Mhz, nxT1/J1, nxE1). Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS/PRBS generation/detection, TAOS, DMO, and diagnostic loopback modes. APPLICATIONS • T1 Digital Cross Connects (DSX-1) • ISDN Primary Rate Interface • CSU/DSU E1/T1/J1 Interface • T1/E1/J1 LAN/WAN Routers • Public Switching Systems and PBX Interfaces • T1/E1/J1 Multiplexer and Channel Banks • Integrated Multi-Service Access Platforms (IMAPs) • Integrated Access Devices (IADs) • Inverse Multiplexing for ATM (IMA) • Wireless Base Stations FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH314 TCLK_n TPOS_n TNEG_n TxON RPOS_n RCLK_n RNEG_n ICT TEST ATP_TIP ATP_RING 1 of 14 Channels Driver Monitor HDB3/B8ZS Encoder Tx/Rx Jitter Attenuator Timing Control Tx Pulse Shaper & Pattern Gen Remote Loopback Digital Loopback QRSS Generation & Detection Line Driver Analog Loopback HDB3/B8ZS Decoder Tx/Rx Jitter Attenuator Clock & Data Recovery Peak Detector & Slicer AIS & LOS Detector Test Microprocessor Interface Programmable Master Clock Synthesizer DMO TTIP_n TRING_n RTIP_n RRING_n RLOS RCLKOUT RxON RxTSEL 8kHzOUT MCLKE1out MCLKT1out MCLKE1Nout MCLKT1Nout Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page XRT83VSH314 REV. 1.0.1 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 28 TABLE 9: RANDOM BIT SEQUENCE POLYNOMIALS ........................................................................................................................... 28 4.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 28 4.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 28 TABLE 10: SHORT HAUL LINE BUILD OUT ....................................................................................................................................... 28 4.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 29 FIGURE 18. ARBITRARY PULSE SEGMENT ASSIGNMENT .................................................................................................................. 29 4.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE ................................................................................. 29 TABLE 11: TYPICAL ROM VALUES.................................................................................................................................................. 30 4.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30 4.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 30 FIGURE 19. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 30 5.0 T1/E1 APPLICATIONS ........................................................................................................................ 31 5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 31 5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 31 FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 31 5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 31 FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK.................................................................................................... 31 5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 32 FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 32 5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 32 FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ........................................................................................................ 32 5.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 33 FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ..................................................................................... 33 TABLE 12: CHIP SELECT ASSIGNMENTS.......................................................................................................................................... 33 5.3 LINE CARD REDUNDANCY .......................................................................................................................... 34 5.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 34 5.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 34 FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 34 5.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 34 FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 35 5.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 35 5.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36 FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY...................................................... 36 5.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 37 FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY........................................................ 37 5.4 POWER FAILURE PROTECTION .................................................................................................................. 38 5.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38 5.6 NON-INTRUSIVE MONITORING .................................................................................................................... 38 FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION .............................................................. 38 5.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 39 FIGURE 30. ATP TESTING BLOCK DIAGRAM..................................................................................................................................... 39 FIGURE 31. TIMING DIAGRAM FOR ATP TESTING ........................................................................................................................... 39 5.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 39 5.7.2 RECEIVER RTIP AND RRING .................................................................................................................................... 40 6.0 MICROPROCESSOR INTERFACE BLOCK ....................................................................................... 41 TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 41 FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK.................................................................. 41 6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 42 TABLE 14: XRT84SH314S MICROPROCESSOR INTERFACE SIGNALS COMMON TO BOTH INTEL AND MOTOROLA MODES.................... 42 TABLE 15: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS .................................................................................................... 42 TABLE 16: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ........................................................................................... 43 6.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .............................................................. 44 FIGURE 33. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................................ 45 TABLE 17: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS........................................................................................ 45 6.3 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 46 FIGURE 34. MOTOROLA MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................... 47 TABLE 18: MOTOROLA MPC86X MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS................................................................ 47 FIGURE 35. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................ 48 TABLE 19: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS........................................................................ 48 7.0 REGISTER DESCRIPTIONS ............................................................................................................... 49 TABLE 20: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]) ................................................................................................... 49 TABLE 21: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION ................................................................................................... 49 TABLE 22: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION ..................................................................................................... 50 II 5 Page REV. 1.0.1 RECEIVER SECTION NAME PIN RNEG13 RNEG12 RNEG11 RNEG10 RNEG9 RNEG8 RNEG7 RNEG6 RNEG5 RNEG4 RNEG3 RNEG2 RNEG1 RNEG0 AA14 Y21 P21 N21 H21 G21 C14 C10 F3 G3 N3 P3 Y3 AA10 RTIP13 RTIP12 RTIP11 RTIP10 RTIP9 RTIP8 RTIP7 RTIP6 RTIP5 RTIP4 RTIP3 RTIP2 RTIP1 RTIP0 AC14 Y23 T23 P23 G23 E23 A14 A9 E1 G1 P1 T1 Y1 AC9 RRING13 RRING12 RRING11 RRING10 RRING9 RRING8 RRING7 RRING6 RRING5 RRING4 RRING3 RRING2 RRING1 RRING0 AC13 W23 U23 N23 H23 D23 A13 A10 D1 H1 N1 U1 W1 AC10 XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT TYPE O DESCRIPTION RNEG/LCV_OF Output In dual rail mode, this pin is the receive negative data output. In single rail mode, this pin can either be a Line Code Violation or Overflow indicator. If LCV is selected by software and if a line code violation, a bi-polar violation, or excessive zeros occur, the LCV pin will pull "High" for a minimum of one RCLK cycle. LCV will remain "High" until there are no more violations. However, if OF is selected the LCV pin will pull "High" if the internal LCV counter is satu- rated. The LCV pin will remain "High" until the LCV counter is reset. I Receive Differential Tip Input RTIP is the positive differential input from the line interface. Along with the RRING signal, these pins should be coupled to a 1:1 transformer for proper operation. I Receive Differential Ring Input RRING is the negative differential input from the line interface. Along with the RTIP signal, these pins should be coupled to a 1:1 transformer for proper oper- ation. 8 11 Page

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