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PDF XRT83VSH28 Data sheet ( Hoja de datos )

Número de pieza XRT83VSH28
Descripción 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
Fabricantes Exar Corporation 
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PRELIMINARY
XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
AUGUST 2006
REV. P1.0.0
GENERAL DESCRIPTION
The XRT83VSH28 is a fully integrated 8-channel
short-haul line interface unit (LIU) that operates from
a 1.8V and a 3.3V power supply. Using internal
termination, the LIU provides one bill of materials to
operate in E1 75or 120mode with minimum
external components. The LIU features are
programmed through a standard parallel or serial
microprocessor interface. EXAR’s LIU has patented
high impedance circuits that allow the transmitter
outputs and receiver inputs to be high impedance
when experiencing a power failure or when the LIU is
powered off. Key design features within the LIU
optimize 1:1 or 1+1 redundancy and non-intrusive
monitoring applications to ensure reliability without
using relays.
The on-chip clock synthesizer generates an E1 clock
reference.
Additional features include RLOS, a 16-bit LCV
counter for each channel, AIS, QRSS generation/
detection, TAOS, DMO, and diagnostic loopback
modes.
APPLICATIONS
ISDN Primary Rate Interface
CSU/DSU E1 Interface
E1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
E1 Multiplexer and Channel Banks
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH28 E1 LIU (HOST MODE)
MCLKE1
TPOS_n/ TDATA_n
TNEG_n/ CODES_n
TCLK_n
RCLK_n
RNEG_n/ LCV_n
RPOS_n/ RDATA_n
RLOS_n
HW/ HOST
WR_R/W
RD_ DS
ALE- AS
CS
RDY_ DTACK/ SDO
INT
SER_ PAR
MASTER CLOCK SYNTHESIZER
1 of 8 channels, CHANNEL_n
QRSS
PATTERN
GENERATOR
HDB3/
ENCODER
TX/ RX JITTER
ATTENUATOR
TAOS
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
DRIVE
MONITOR
LINE
DRIVER
QRSS
DETECTOR
Remote
Loopback
Digital
Loopback
Analog
Loopback
HDB3/
DECODER
TX/ RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LOS
DETECTOR
AIS
DETECTOR
PEAK
DETECTOR
& SLICER
TEST
MICROPROCESSOR/ SERIAL INTERFACE CONTROLLER
MCLKOUT
D M O_ n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
ICT
µ PTS1
µ PTS2
D[7:0]
µ PCLK/ SCLK
A[7:0]/ SDI
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XRT83VSH28 pdf
PRELIMINARY
XRT83VSH28
REV. P1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH28 E1 LIU (HOST MODE)........................................................................................ 1
FIGURE 2. BLOCK DIAGRAM OF THE XRT83VSH28 E1 LIU (HARDWARE MODE) ............................................................................... 2
FEATURES ..................................................................................................................................................... 3
ORDERING INFORMATION .................................................................................................................... 3
PIN DESCRIPTION BY FUNCTION................................................................................... 5
RECEIVE SECTION ......................................................................................................................................... 5
TRANSMIT SECTION ....................................................................................................................................... 8
PARALLEL MICROPROCESSOR INTERFACE..................................................................................................... 10
JITTER ATTENUATOR .................................................................................................................................... 12
CLOCK SYNTHESIZER................................................................................................................................... 12
ALARM FUNCTIONS/REDUNDANCY SUPPORT ................................................................................................. 14
SERIAL MICROPROCESSOR INTERFACE ......................................................................................................... 16
POWER AND GROUND .................................................................................................................................. 16
FUNCTIONAL DESCRIPTION ......................................................................................... 19
1.0 HARDWARE MODE VS HOST MODE ................................................................................................ 19
1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 19
TABLE 1: DIFFERENCES BETWEEN HARDWARE MODE AND HOST MODE .......................................................................................... 19
2.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 20
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH...................................................................................................... 20
2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 20
2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 20
TABLE 2: SELECTING THE INTERNAL IMPEDANCE ............................................................................................................................. 20
FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 20
2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 21
TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR ............................................................................................. 21
FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR ....................................................................... 21
2.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22
FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 22
FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 22
TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 22
2.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 23
FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 23
2.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 23
FIGURE 9. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN .................................................................................... 23
2.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 23
2.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24
2.4 HDB3 DECODER ............................................................................................................................................ 25
2.5 RPOS/RNEG/RCLK ........................................................................................................................................ 25
FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN................................................................................... 25
FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN...................................................................................... 25
2.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 26
FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION ............................................................................................ 26
3.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 27
FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH................................................................................................... 27
3.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 27
FIGURE 14. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 27
FIGURE 15. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 27
TABLE 5: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 28
3.2 HDB3 ENCODER ............................................................................................................................................ 28
TABLE 6: EXAMPLES OF HDB3 ENCODING...................................................................................................................................... 28
3.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 29
TABLE 7: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 29
3.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 29
FIGURE 16. TAOS (TRANSMIT ALL ONES)...................................................................................................................................... 29
3.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 29
3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 29
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 30
3.5.2 QRSS GENERATION.................................................................................................................................................. 30
TABLE 8: RANDOM BIT SEQUENCE POLYNOMIALS ........................................................................................................................... 30
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XRT83VSH28 arduino
REV. P1.0.0
TRANSMIT SECTION
PRELIMINARY
XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
SIGNAL NAME
BGA
LEAD #
TCLKE/µPTS2 L15
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
TPOS0
TPOS1
TPOS2
TPOS3
TPOS4
TPOS5
TPOS6
TPOS7
TNEG0
TNEG1
TNEG2
TNEG3
TNEG4
TNEG5
TNEG6
TNEG7
E3
G4
F17
C16
R2
N2
N16
P16
E2
F3
F15
E16
P2
N4
R15
P17
C5
A4
B14
D14
V4
U5
V15
T14
C4
B5
D13
B15
U4
V5
U14
R14
TYPE
DESCRIPTION
I Transmit Clock Edge
Hardware Mode
This pin is used to select which edge of the transmit clock is used to sample data
on the transmitter on the TPOS/TNEG inputs. By default, data is sampled on the
falling edge. To sample data on the rising edge, this pin must be pulled "High".
Host Mode
µPTS[2:1] pins are used to select the type of microprocessor to be used for Host
communication.
"00" = 8051 Intel Asynchronous
"01" = 68K Motorola Asynchronous
"11" = MPC8xx Power PC Synchronous
NOTE: This pin is internally pulled “Low” with a 50kresistor.
O Transmit Differential Tip Output
TTIP is the positive differential output to the line interface. Along with the TRING
signal, these pins should be coupled to a 1:2 step up transformer for proper opera-
tion.
O Transmit Differential Ring Output
TRING is the negative differential output to the line interface. Along with the TTIP
signal, these pins should be coupled to a 1:2 step up transformer for proper opera-
tion.
I TPOS/TDATA Input
Transmit digital input pin. In dual rail mode, this pin is the transmit positive data
input. In single rail mode, this pin is the transmit non-return to zero (NRZ) data
input.
NOTE: Internally pulled "Low" with a 50Kresistor.
I Transmitter Negative NRZ Data Input
In dual rail mode, this signal is the negative-rail input data for the transmitter. In
single rail mode, this pin can be left unconnected while in Host mode. However, in
Hardware mode, this pin is used to select the type of encoding/decoding for the E1
data format. Connecting this pin “Low” enables HDB3. Connecting this pin “High”
selects AMI data format.
NOTE: Internally pulled “Low” with a 50kresistor.
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