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PDF XRT83SL34 Data sheet ( Hoja de datos )

Número de pieza XRT83SL34
Descripción QUAD T1/E1/J1 SH TRANSCEIVER
Fabricantes Exar Corporation 
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PRELIMINARY
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FEBRUARY 2004
REV. P1.0.8
GENERAL DESCRIPTION
The XRT83SL34 is a fully integrated Quad (four
channel) short-haul line interface unit for T1
(1.544Mbps) 100, E1 (2.048Mbps) 75or 120, or
J1 110applications.
In T1 applications, the XRT83SL34 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements. It
also provides programmable transmit pulse
generators for each channel that can be used for
output pulse shaping allowing performance
improvement over a wide variety of conditions.
The XRT83SL34 provides both a parallel Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit path
with loop bandwidths of less than 3Hz. The
XRT83SL34 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75Ω,
100Ω, 110and 120for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL34 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
T P O S _n/T D A T A _n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
R P O S _ n/R D A T A _n
RLOS_n
HW /HOST
W R_R/W
RD_DS
ALE-AS
CS
RDY_DTACK
IN T
MASTER CLOCK SYNTHESIZER
One of four channels, CHANNEL_n - (n= 0:3)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/R X JIT TER
ATTENUATOR
TAOS
ENABLE
T IM IN G
CONTROL
DFM
D R IV E
M O N IT O R
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
D IG ITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/R X JIT TER
ATTENUATOR
T IMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
E Q U A L IZ E R
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
E Q U A L IZ E R
TEST
MICROPROCESSOR CONT ROLLER
MCLKOUT
DMO_n
TTIP_n
T R IN G _n
TXON_n
RTIP_n
RRING_n
ICT
µPTS1
µPTS2
D[7:0]
µPCLK
A[7:0]
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT83SL34 pdf
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.8
Figure 12. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. 28
TRANSMITTER (CHANNELS 0 - 3) ............................................................................................................ 29
Transmit Termination Mode ...................................................................................................................... 29
External Transmit Termination Mode ........................................................................................................ 29
Figure 13. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 29
TABLE 8: TRANSMIT TERMINATION CONTROL ....................................................................................... 29
TABLE 9: TERMINATION SELECT CONTROL .......................................................................................... 29
REDUNDANCY APPLICATIONS ............................................................................................................. 30
TABLE 10: TRANSMIT TERMINATION CONTROL ..................................................................................... 30
TABLE 11: TRANSMIT TERMINATIONS ................................................................................................... 30
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 31
Figure 14. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 32
Figure 15. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............. 32
Figure 16. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 33
Figure 17. Simplified Block Diagram - Receive Section for N+1 Redundancy .......................... 34
PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 35
TRANSMIT ALL ONES (TAOS) .................................................................................................................... 35
NETWORK LOOP CODE DETECTION AND TRANSMISSION .............................................................................. 35
TABLE 12: PATTERN TRANSMISSION CONTROL ..................................................................................... 35
TABLE 13: LOOP-CODE DETECTION CONTROL ..................................................................................... 35
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 36
LOOP-BACK MODES ................................................................................................................................... 37
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ........................................................................ 37
TABLE 15: LOOP-BACK CONTROL IN HOST MODE ................................................................................. 37
LOCAL ANALOG LOOP-BACK (ALOOP) ....................................................................................................... 38
REMOTE LOOP-BACK (RLOOP) ................................................................................................................. 38
Figure 18. Local Analog Loop-back signal flow ........................................................................... 38
Figure 19. Remote Loop-back mode with jitter attenuator selected in receive path ................. 38
DIGITAL LOOP-BACK (DLOOP) .................................................................................................................. 39
Figure 20. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 39
Figure 21. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 39
DUAL LOOP-BACK ...................................................................................................................................... 40
Figure 22. Signal flow in Dual loop-back mode ............................................................................ 40
MICROPROCESSOR PARALLEL INTERFACE .............................................................. 41
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ........................................................... 41
MICROPROCESSOR REGISTER TABLES ........................................................................................................ 42
TABLE 17: MICROPROCESSOR REGISTER ADDRESS ............................................................................. 42
TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION ................................................................. 42
MICROPROCESSOR REGISTER DESCRIPTIONS ............................................................................................. 45
TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ........................................................... 45
TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ........................................................... 46
TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ........................................................... 48
TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ........................................................... 50
TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ........................................................... 52
TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ........................................................... 53
TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ........................................................... 55
TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ........................................................... 56
TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ........................................................... 57
TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ........................................................... 57
TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION ......................................................... 58
TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION ......................................................... 58
TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION ......................................................... 59
TABLE 32: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION ......................................................... 59
TABLE 33: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION ......................................................... 60
II

5 Page





XRT83SL34 arduino
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.8
MICROPROCESSOR INTERFACE
SIGNAL NAME
HW_HOST
WR_R/W
TAOS_0
RD_DS
TAOS_1
ALE_AS
TAOS_2
CS
TAOS_3
RDY_DTACK
RXMUTE
PIN #
68
69
69
70
70
71
71
72
72
73
73
TYPE
I
I
I
I
I
O
I
DESCRIPTION
Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie
“High” to select Hardware mode.
For Host mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50kresistor.
Write Input (Read/Write) - Host mode
Intel bus timing: A “Low” pulse on WR selects a write operation when CS
pin is “Low”.
Motorola bus timing: A “High” pulse on R/W selects a read operation and a
“Low” pulse on R/W selects a write operation when CS is “Low”.
Transmit All “Ones” Channel_0 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kresistor.
Read Input (Data Strobe) - Host Mode
Intel bus timing: A “Low” pulse on RD selects a read operation when the CS
pin is “Low”.
Motorola bus timing: A “Low” pulse on DS indicates a read or write opera-
tion when the CS pin is “Low”.
Transmit All “Ones” Channel_1 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kresistor.
Address Latch Input (Address Strobe) - Host Mode
Intel bus timing: The address inputs are latched into the internal register on
the falling edge of ALE.
Motorola bus timing: The address inputs are latched into the internal regis-
ter on the falling edge of AS.
Transmit All “Ones” Channel_2 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kresistor.
Chip Select Input - Host Mode
This signal must be “Low” in order to access the parallel port.
Transmit All “Ones” Channel_3 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kresistor.
Ready Output (Data Transfer Acknowledge Output) - Host Mode
Intel bus timing: RDY is asserted “High” to indicate the device has com-
pleted a read or write operation.
Motorola bus timing: DTACK is asserted "Low" to indicate the device has
completed a read or write cycle.
Receive Muting - Hardware mode
See “Receive Muting - Hardware mode” on page 5.
NOTE: Internally pulled “Low” with a 50kresistor.
8

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