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PDF XRT83SL30 Data sheet ( Hoja de datos )
| Número de pieza | XRT83SL30 | |
| Descripción | SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MAY 2003
REV. P1.0.4
GENERAL DESCRIPTION
The XRT83SL30 is a fully integrated single-channel
short-haul line interface unit for T1(1.544Mbps) 100Ω,
E1(2.048Mbps) 75Ω or 120Ω and J1 110Ω applica-
tions.
In T1 applications, the XRT83SL30 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements.
The XRT83SL30 provides both Serial Host micropro-
cessor interface and Hardware Mode for program-
ming and control. Both B8ZS and HDB3 encoding
and decoding functions are included and can be dis-
abled as required. On-chip crystal-less jitter attenua-
tor with a 32 or 64 bit FIFO can be placed either in the
receive or the transmit path with loop bandwidths of
less than 3Hz. The XRT83SL30 provides a variety of
loop-back and diagnostic features as well as transmit
driver short circuit detection and receive loss of signal
monitoring. It supports internal impedance matching
for 75Ω, 100Ω, 110Ω and 120Ω for both transmitter
and receiver. For the receiver this is accomplished
with internal resistors or through the combination of
one single fixed value external resistor and program-
mable internal resistors. In the absence of the power
supply, the transmit output and receive input are tri-
stated allowing for redundancy applications. The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a va-
riety of external clock sources.
APPLICATIONS
• T1 Digital Cross-Connects (DSX-1)
• ISDN Primary Rate Interface
• CSU/DSU E1/T1/J1 Interface
• T1/E1/J1 LAN/WAN Routers
• Public switching Systems and PBX Interfaces
• T1/E1/J1 Multiplexer and Channel Banks
FEATURES
(See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
HW/HOST
CS
INT
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
HDB3/
B8ZS
ENCODER
TAOS
ENABLE
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
DRIVE
MONITOR
LINE
DRIVER
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
Serial Interface
TEST
MCLKOUT
DMO
TTIP
TRING
TXON
RTIP
RRING
AISD
ICT
SDO
SCLK
SDI
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
áç
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.4
Internal Receive Termination Mode ................................................................................................................. 26
TABLE 6: RECEIVE TERMINATION CONTROL ................................................................................................ 26
Figure 11. Simplified Diagram for the Internal Receive and Transmit Termination Mode .............. 26
TABLE 7: RECEIVE TERMINATIONS ............................................................................................................. 27
Figure 12. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ................... 27
TRANSMITTER ........................................................................................................................................ 28
Transmit Termination Mode ............................................................................................................................. 28
External Transmit Termination Mode ............................................................................................................... 28
Figure 13. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ......................... 28
TABLE 8: TRANSMIT TERMINATION CONTROL ............................................................................................. 28
TABLE 9: TERMINATION SELECT CONTROL ................................................................................................. 28
REDUNDANCY APPLICATIONS ............................................................................................................. 29
TABLE 10: TRANSMIT TERMINATION CONTROL ........................................................................................... 29
TABLE 11: TRANSMIT TERMINATIONS ......................................................................................................... 29
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 30
Figure 14. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ............. 31
Figure 15. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .................... 31
Figure 16. Simplified Block Diagram - Transmit Section for N+1 Redundancy ............................... 32
Figure 17. Simplified Block Diagram - Receive Section for N+1 Redundancy ................................. 33
PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 34
TRANSMIT ALL ONES (TAOS) .................................................................................................................... 34
NETWORK LOOP CODE DETECTION AND TRANSMISSION .............................................................................. 34
TABLE 12: PATTERN TRANSMISSION CONTROL ............................................................................................ 34
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 35
TABLE 13: LOOP-CODE DETECTION CONTROL ........................................................................................... 35
LOOP-BACK MODES ................................................................................................................................... 37
LOCAL ANALOG LOOP-BACK (ALOOP) ....................................................................................................... 37
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE .............................................................................. 37
TABLE 15: LOOP-BACK CONTROL IN HOST MODE ........................................................................................ 37
Figure 18. Local Analog Loop-back signal flow .................................................................................. 37
REMOTE LOOP-BACK (RLOOP) ................................................................................................................. 38
Figure 19. Remote Loop-back mode with jitter attenuator selected in receive path ....................... 38
Figure 20. Remote Loop-back mode with jitter attenuator selected in Transmit path .................... 38
DIGITAL LOOP-BACK (DLOOP) .................................................................................................................. 39
DUAL LOOP-BACK ...................................................................................................................................... 39
Figure 21. Digital Loop-back mode with jitter attenuator selected in Transmit path ...................... 39
Figure 22. Signal flow in Dual loop-back mode ................................................................................... 39
HOST MODE SERIAL INTERFACE OPERATION ........................................................... 40
USING THE MICROPROCESSOR SERIAL INTERFACE ...................................................................................... 40
Figure 23. Microprocessor Serial Interface Data Structure ................................................................ 41
TABLE 16: MICROPROCESSOR REGISTER ADDRESS ................................................................................... 42
TABLE 17: MICROPROCESSOR REGISTER BIT MAP ..................................................................................... 42
TABLE 18: MICROPROCESSOR REGISTER #0 BIT DESCRIPTION .................................................................... 44
TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION .................................................................... 44
TABLE 20: MICROPROCESSOR REGISTER #2 BIT DESCRIPTION .................................................................... 47
TABLE 21: MICROPROCESSOR REGISTER #3 BIT DESCRIPTION .................................................................... 49
TABLE 22: MICROPROCESSOR REGISTER #4 BIT DESCRIPTION .................................................................... 51
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION .................................................................... 52
TABLE 24: MICROPROCESSOR REGISTER #6 BIT DESCRIPTION .................................................................... 54
TABLE 25: MICROPROCESSOR REGISTER #7 BIT DESCRIPTION .................................................................... 55
TABLE 26: MICROPROCESSOR REGISTER #8 BIT DESCRIPTION .................................................................... 55
TABLE 27: MICROPROCESSOR REGISTER #9 BIT DESCRIPTION .................................................................... 56
TABLE 28: MICROPROCESSOR REGISTER #10 BIT DESCRIPTION .................................................................. 56
TABLE 29: MICROPROCESSOR REGISTER #11 BIT DESCRIPTION .................................................................. 56
TABLE 30: MICROPROCESSOR REGISTER #12 BIT DESCRIPTION .................................................................. 57
II
5 Page 
áç
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.4
JITTER ATTENUATOR
SIGNAL NAME
JABW
JASEL1
JASEL0
PIN #
46
47
48
TYPE
I
I
DESCRIPTION
Jitter Attenuator Bandwidth
In Hardware and E1 mode, when JABW=”0” the jitter attenuator bandwidth is
10Hz (normal mode). Setting JABW to “1” selects a 1.5Hz Bandwidth for the
Jitter Attenuator and the FIFO length will be automatically set to 64 bits. In T1
mode the Jitter Attenuator Bandwidth is always set to 3Hz, and the state of
this pin has no effect on the Bandwidth. See table under JASEL[1:0] pin,
below.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Jitter Attenuator select pin 1
Jitter Attenuator select pin 0
In Hardware Mode, JASEL0, JASEL1 and JABW pins are used to place the
jitter attenuator in the transmit path, the receive path or to disable it and set
the jitter attenuator bandwidth and FIFO size per the following table.
JABW JASEL1 JASEL0 JA Path
0 0 0 Disabled
JA BW (Hz)
T1 E1
------ ------
FIFO Size
T1/E1
------
0
0
1
Transmit
3
10
32/32
0
1
0
Receive
3
10
32/32
0
1
1
Receive
3
10
64/64
1
0
0
Disabled ------ ------
--------
1
0
1
Transmit
3
1.5
32/64
1
1
0
Receive
3
1.5
32/64
1
1
1
Receive
3
1.5
64/64
NOTE: These pins are internally pulled "Low" with 50kΩ resistors.
8
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| PDF Descargar | [ Datasheet XRT83SL30.PDF ] | |
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