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PDF XRT83SL28 Data sheet ( Hoja de datos )
| Número de pieza | XRT83SL28 | |
| Descripción | 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
APRIL 2005
GENERAL DESCRIPTION
The XRT83SL28 is a fully integrated 8-channel E1
short-haul LIU which optimizes system cost and
performance by offering key design features. The
XRT83SL28 operates from a single 3.3V power
supply. The LIU features are programmed through a
standard serial microprocessor interface or hardware
control. EXAR’s LIU has patented high impedance
circuits that allow the transmitter outputs and receiver
inputs to be high impedance when experiencing a
power failure or when the LIU is powered off. Key
design features within the LIU optimize 1:1 or 1+1
redundancy and non-intrusive monitoring applications
to ensure reliability without using relays.
REV. 1.0.0
Additional features include TAOS for transmit and
receive, RLOS, LCV, AIS, DMO, and diagnostic
loopback modes.
APPLICATIONS
• ISDN Primary Rate Interface
• CSU/DSU E1 Interface
• E1 LAN/WAN Routers
• Public Switching Systems and PBX Interfaces
• E1 Multiplexer and Channel Banks
• Integrated Multi-Service Access Platforms (IMAPs)
• Integrated Access Devices (IADs)
• Inverse Multiplexing for ATM (IMA) Wireless Base
Stations
FIGURE 1. HOST MODE BLOCK DIAGRAM OF THE XRT83SL28
TTPCOLKS
TNEG
RCLK
RPOS
RNEG/LCV
1 of 8 Channels
HDB3
Encoder
Timing
Control
Remote
Loopback
Jitter
Attenuator
(Rx or Tx)
Digital
Loopback
HDB3
Decoder
Clock & Data
Recovery
Tx Pulse
Shaper
Peak
Detector
& Slicer
Driver
Monitor
Line
Driver
Analog
Loopback
Rx
Equalizer
DMO
TTIP
TRING
RTIP
RRING
RLOS
AIS & LOS
Detector
ICT Test
Serial Microprocessor
Interface
Clock Distribution
TxOE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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REV. 1.0.0
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS........................................................................................................................................... 1
FIGURE 1. HOST MODE BLOCK DIAGRAM OF THE XRT83SL28 ......................................................................................................... 1
FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 ................................................................................................ 2
FEATURES ..................................................................................................................................................... 3
PRODUCT ORDERING INFORMATION.................................................................................................. 3
FIGURE 3. PIN OUT OF THE XRT83SL28 ......................................................................................................................................... 4
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS .......................................................................................................... 5
SERIAL MICROPROCESSOR INTERFACE............................................................................................................ 5
RECEIVER SECTION ....................................................................................................................................... 6
TRANSMITTER SECTION.................................................................................................................................. 7
CONTROL FUNCTION...................................................................................................................................... 8
POWER AND GROUND (HOST AND HARDWARE MODES).................................................................................... 9
HARDWARE MODE INTERFACE ....................................................................................................................... 10
1.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 14
FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING)................................................. 14
1.1 INTERNAL TERMINATION ............................................................................................................................ 14
TABLE 1: SELECTING THE INTERNAL IMPEDANCE ............................................................................................................................. 14
FIGURE 5. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 14
1.2 PEAK DETECTOR/DATA SLICER ................................................................................................................. 15
1.3 CLOCK AND DATA RECOVERY ................................................................................................................... 15
FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 15
FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 15
TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 15
1.4 RECEIVE SENSITIVITY .................................................................................................................................. 16
FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 16
1.5 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 16
1.5.1 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 17
1.5.2 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 17
1.5.3 LCV (LINE CODE VIOLATION DETECTION) ............................................................................................................ 17
1.6 RECEIVE JITTER ATTENUATOR .................................................................................................................. 17
1.7 HDB3 DECODER ............................................................................................................................................ 18
1.8 ARAOS (AUTOMATIC RECEIVE ALL ONES) ............................................................................................... 18
FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION ................................................................................................ 18
1.9 RPOS/RNEG/RCLK ........................................................................................................................................ 18
FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN................................................................................... 18
FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN...................................................................................... 19
2.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 20
FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH................................................................................................... 20
2.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 20
FIGURE 13. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 20
FIGURE 14. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 20
TABLE 3: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 21
2.2 HDB3 ENCODER ............................................................................................................................................ 21
TABLE 4: EXAMPLES OF HDB3 ENCODING...................................................................................................................................... 21
2.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 21
TABLE 5: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 21
2.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 22
FIGURE 15. TAOS (TRANSMIT ALL ONES)ATAOS (AUTOMATIC TRANSMIT ALL ONES) .................................................................... 22
2.5 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ............................................................................................ 22
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 22
2.6 TRANSMITTER POWER DOWN IN HARDWARE MODE ............................................................................. 22
2.7 DMO (DRIVER MONITOR OUTPUT) ............................................................................................................. 22
2.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 23
FIGURE 17. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 23
3.0 E1 APPLICATIONS ............................................................................................................................. 24
3.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 24
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REV. 1.0.0
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
POWER AND GROUND (HOST AND HARDWARE MODES)
NAME
PIN TYPE
DESCRIPTION
TVDD7
TVDD6
TVDD5
TVDD4
TVDD3
TVDD2
TVDD1
TVDD0
79 PWR Transmit Analog Power Supply (3.3V ±5%)
83 TVDD can be shared with DVDD. However, it is recommended that TVDD be
98 isolated from the analog power supply RVDD. For best results, use an internal
102
30
power plane for isolation. If an internal power plane is not available, a ferrite
bead can be used. Each power supply pin should be bypassed to ground
through an external 0.1µF capacitor.
26
11
7
RVDD2
RVDD1
127 PWR Receive Analog Power Supply (3.3V ±5%)
54 RVDD should not be shared with other power supplies. It is recommended that
RVDD be isolated from the digital power supply DVDD and the analog power
supply TVDD. For best results, use an internal power plane for isolation. If an
internal power plane is not available, a ferrite bead can be used. Each power
supply pin should be bypassed to ground through an external 0.1µF capacitor.
DVDD2
129 PWR Digital Power Supply (3.3V ±5%)
DVDD1
DVDDcore
52
93
DVDD should be isolated from the analog power supplies except for TVDD.
For best results, use an internal power plane for isolation. If an internal power
plane is not available, a ferrite bead can be used. Every two DVDD power sup-
ply pins should be bypassed to ground through at least one 0.1µF capacitor.
AVDD
16 PWR Analog Power Supply (3.3V ±5%)
AVDD should be isolated from the digital power supplies. For best results, use
an internal power plane for isolation. If an internal power plane is not available,
a ferrite bead can be used. Each power supply pin should be bypassed to
ground through at least one 0.1µF capacitor.
TGND7
TGND6
TGND5
TGND4
TGND3
TGND2
TGND1
TGND0
77 GND Transmit Analog Ground
85 It’s recommended that all ground pins of this device be tied together.
96
104
32
24
13
5
RGND2
RGND1
126 GND Receive Analog Ground
55 It’s recommended that all ground pins of this device be tied together.
DGND2
DGND1
DGNDcore
128
53
88
GND
Digital Ground
It’s recommended that all ground pins of this device be tied together.
AGND
18 GND Analog Ground
It’s recommended that all ground pins of this device be tied together.
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT83SL28.PDF ] | |
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