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PDF XRT83SH38 Data sheet ( Hoja de datos )
| Número de pieza | XRT83SH38 | |
| Descripción | 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
MAY 2006
REV. 1.0.3
GENERAL DESCRIPTION
The XRT83SH38 is a fully integrated 8-channel short-
haul line interface unit (LIU) that operates from a
single 3.3V power supply. Using internal termination,
the LIU provides one bill of materials to operate in T1,
E1, or J1 mode with minimum external components.
The LIU features are programmed through a standard
microprocessor interface, serial interface or
controlled through Hardware mode. EXAR’s LIU has
patented high impedance circuits that allow the
transmitter outputs and receiver inputs to be high
impedance when experiencing a power failure or
when the LIU is powered off. Key design features
within the LIU optimize 1:1 or 1+1 redundancy and
non-intrusive monitoring applications to ensure
reliability without using relays.
The on-chip clock synthesizer generates T1/E1/J1
clock rates from a selectable external clock frequency
and outputs a clock reference of the line rate chosen.
Additional features include RLOS, a 16-bit LCV
counter for each channel, AIS, QRSS generation/
detection, TAOS, DMO, and diagnostic loopback
modes.
APPLICATIONS
• T1 Digital Cross-Connects (DSX-1)
• ISDN Primary Rate Interface
• CSU/DSU E1/T1/J1 Interface
• T1/E1/J1 LAN/WAN Routers
• Public switching Systems and PBX Interfaces
• T1/E1/J1 Multiplexer and Channel Banks
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SH38 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE-AS
CS
RDY_DTACK/SDO
INT
SER_PAR
MASTER CLOCK SYNTHESIZER
1 of 8 channels, CHANNEL_n
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TAOS
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
DRIVE
MONITOR
LINE
DRIVER
QRSS
DETECTOR
Remote
Loopback
Digital
Loopback
Analog
Loopback
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LOS
DETECTOR
AIS
DETECTOR
PEAK
DETECTOR
& SLICER
TEST
MICROPROCESSOR/SERIAL INTERFACE CONTROLLER
MCLKOUT
DMO_n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
ICT
µPTS1
µPTS2
D[7:0]
µPCLK/SCLK
A[7:0]/SDI
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.3
XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
APPLICATIONS ............................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SH38 T1/E1/J1 LIU (HOST MODE)....................................................................................... 1
FIGURE 2. BLOCK DIAGRAM OF THE XRT83SH38 T1/E1/J1 LIU (HARDWARE MODE) .............................................................................. 2
FEATURES..................................................................................................................................................................... 3
ORDERING INFORMATION .................................................................................................................... 3
PIN DESCRIPTION BY FUNCTION............................................................................................... 5
RECEIVE SECTION ......................................................................................................................................................... 5
TRANSMIT SECTION ....................................................................................................................................................... 8
MICROPROCESSOR INTERFACE .................................................................................................................................... 10
JITTER ATTENUATOR.................................................................................................................................................... 12
CLOCK SYNTHESIZER .................................................................................................................................................. 12
ALARM FUNCTIONS/REDUNDANCY SUPPORT................................................................................................................. 14
SERIAL PORT AND JTAG............................................................................................................................................... 16
POWER AND GROUND.................................................................................................................................................. 17
FUNCTIONAL DESCRIPTION ...................................................................................................... 19
1.0 HARDWARE MODE VS HOST MODE ................................................................................................ 19
1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 19
TABLE 1: DIFFERENCES BETWEEN HARDWARE MODE AND HOST MODE................................................................................................. 19
2.0 MASTER CLOCK GENERATOR ......................................................................................................... 20
FIGURE 3. TWO INPUT CLOCK SOURCE................................................................................................................................................. 20
FIGURE 4. ONE INPUT CLOCK SOURCE ................................................................................................................................................. 20
TABLE 2: MASTER CLOCK GENERATOR ................................................................................................................................................. 20
3.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 21
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 21
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 21
3.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 21
TABLE 3: SELECTING THE INTERNAL IMPEDANCE ................................................................................................................................... 21
FIGURE 6. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 22
3.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 22
TABLE 4: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 22
FIGURE 7. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR ............................................................................. 22
3.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22
FIGURE 8. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 23
FIGURE 9. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................... 23
TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG ................................................................................................................ 23
3.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 23
FIGURE 10. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ............................................................................................ 24
3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 24
FIGURE 11. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN......................................................................................... 24
3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 24
FIGURE 12. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1................................................................................................................ 25
TABLE 6: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 ............................................................................................. 25
3.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 26
3.4 HDB3/B8ZS DECODER .................................................................................................................................. 26
3.5 RPOS/RNEG/RCLK ........................................................................................................................................ 26
FIGURE 13. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 26
FIGURE 14. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 26
3.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 27
FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION................................................................................................... 27
4.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 28
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 28
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 28
FIGURE 17. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK...................................................................................................... 28
FIGURE 18. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK........................................................................................................ 28
TABLE 7: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 29
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 29
TABLE 8: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 29
TABLE 9: EXAMPLES OF B8ZS ENCODING............................................................................................................................................. 29
4.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 30
I
5 Page 
REV. 1.0.3
TRANSMIT SECTION
XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
SIGNAL NAME
BGA
LEAD #
TCLKE/µPTS2 L15
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
TPOS0
TPOS1
TPOS2
TPOS3
TPOS4
TPOS5
TPOS6
TPOS7
TNEG0
TNEG1
TNEG2
TNEG3
TNEG4
TNEG5
TNEG6
TNEG7
E3
G4
F17
C16
R2
N2
N16
P16
E2
F3
F15
E16
P2
N4
R15
P17
C5
A4
B14
D14
V4
U5
V15
T14
C4
B5
D13
B15
U4
V5
U14
R14
TYPE
DESCRIPTION
I Transmit Clock Edge
Hardware Mode
This pin is used to select which edge of the transmit clock is used to sample data
on the transmitter on the TPOS/TNEG inputs. By default, data is sampled on the
falling edge. To sample data on the rising edge, this pin must be pulled "High".
Host Mode
µPTS[2:1] pins are used to select the type of microprocessor to be used for Host
communication.
"00" = 8051 Intel Asynchronous
"01" = 68K Motorola Asynchronous
"10" = x86 Intel Synchronous
"11" = 860 Motorola Synchronous
NOTE: This pin is internally pulled “Low” with a 50kΩ resistor.
O Transmit Differential Tip Output
TTIP is the positive differential output to the line interface. Along with the TRING
signal, these pins should be coupled to a 1:2 step up transformer for proper opera-
tion.
O Transmit Differential Ring Output
TRING is the negative differential output to the line interface. Along with the TTIP
signal, these pins should be coupled to a 1:2 step up transformer for proper opera-
tion.
I TPOS/TDATA Input
Transmit digital input pin. In dual rail mode, this pin is the transmit positive data
input. In single rail mode, this pin is the transmit non-return to zero (NRZ) data
input.
NOTE: Internally pulled "Low" with a 50KΩ resistor.
I Transmitter Negative NRZ Data Input
In dual rail mode, this signal is the negative-rail input data for the transmitter. In
single rail mode, this pin can be left unconnected while in Host mode. However, in
Hardware mode, this pin is used to select the type of encoding/decoding for the E1/
T1 data format. Connecting this pin “Low” enables HDB3 in E1 or B8ZS in T1.
Connecting this pin “High” selects AMI data format.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
8
11 Page | ||
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| PDF Descargar | [ Datasheet XRT83SH38.PDF ] | |
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