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PDF XRT83L34 Data sheet ( Hoja de datos )

Número de pieza XRT83L34
Descripción QUAD T1/E1/J1 LH/SH TRANSCEIVER
Fabricantes Exar Corporation 
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PRELIMINARY
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FEBRUARY 2004
REV. P1.3.4
GENERAL DESCRIPTION
The XRT83L34 is a fully integrated Quad (four
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100, E1 (2.048Mbps) 75or
120Ω, or J1 110applications.
In long-haul applications the XRT83L34 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83L34 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions.
The XRT83L34 provides both a parallel Host
microprocessor interface as well as a Hardware mode
for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83L34 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75Ω,
100Ω, 110and 120for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1 BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
T P O S _n/T D A T A _n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
R P O S _ n/R D A T A _n
RLOS_n
HW /HOST
W R_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
IN T
MASTER CLOCK SYNTHESIZER
One of four channels, CHANNEL_n - (n= 0:3)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/R X JIT TER
ATTENUATOR
TAOS
ENABLE
T IM IN G
CONTROL
DFM
D R IV E
M O N IT O R
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
D IG ITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/R X JIT TER
ATTENUATOR
T IMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
E Q U A L IZ E R
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
E Q U A L IZ E R
TEST
MICROPROCESSOR CONT ROLLER
MCLKOUT
DMO_n
TTIP_n
T R IN G _n
TXON_n
RTIP_n
RRING_n
ICT
µPTS1
µPTS2
D[7:0]
µPCLK
A[7:0]
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT83L34 pdf
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS .............................................................................................................................................. 1
Figure 1 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ............................................ 1
Figure 2 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware Mode) ................................... 2
FEATURES .................................................................................................................................................... 2
ORDERING INFORMATION ...................................................................................................................... 3
Figure 3 Pin Out of the XRT83L34 .................................................................................................... 4
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTION BY FUNCTION ................................................................................... 5
RECEIVE SECTIONS ...................................................................................................................................... 5
TRANSMITTER SECTIONS .............................................................................................................................. 7
MICROPROCESSOR INTERFACE ...................................................................................................................... 9
JITTER ATTENUATOR .................................................................................................................................. 12
CLOCK SYNTHESIZER .................................................................................................................................. 13
ALARM FUNCTION//REDUNDANCY SUPPORT ................................................................................................. 14
POWER AND GROUND ................................................................................................................................. 18
FUNCTIONAL DESCRIPTION ......................................................................................... 19
MASTER CLOCK GENERATOR ...................................................................................................................... 19
Figure 4. Two Input Clock Source .................................................................................................. 19
Figure 5. One Input Clock Source .................................................................................................. 19
RECEIVER ........................................................................................................................ 20
RECEIVER INPUT ......................................................................................................................................... 20
TABLE 1: MASTER CLOCK GENERATOR ............................................................................................... 20
RECEIVE MONITOR MODE ........................................................................................................................... 21
RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... 21
Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... 21
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 22
Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ............... 22
RECEIVE HDB3/B8ZS DECODER ................................................................................................................ 23
RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 23
Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ............................................... 23
Figure 10. Receive Clock and Output Data Timing ....................................................................... 23
JITTER ATTENUATOR .................................................................................................................................. 24
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................. 24
TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ........................................ 24
ARBITRARY PULSE GENERATOR FOR T1 AND E1 .......................................................................................... 25
TRANSMITTER ................................................................................................................. 25
DIGITAL DATA FORMAT ............................................................................................................................... 25
TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 25
Figure 11. Arbitrary Pulse Segment Assignment .......................................................................... 25
TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 26
Figure 12. Transmit Clock and Input Data Timing ........................................................................ 26
TABLE 3: EXAMPLES OF HDB3 ENCODING ........................................................................................... 26
TABLE 4: EXAMPLES OF B8ZS ENCODING ........................................................................................... 26
DRIVER FAILURE MONITOR (DMO) .............................................................................................................. 27
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... 27
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ........................... 27
TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 29
RECEIVER (CHANNELS 0 - 3) ................................................................................................................... 29
Internal Receive Termination Mode .......................................................................................................... 29
TABLE 6: RECEIVE TERMINATION CONTROL .......................................................................................... 29
I

5 Page





XRT83L34 arduino
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
SIGNAL NAME
TCLK_0
PIN #
1
TCLK_1
TCLK_2
TCLK_3
TAOS_0
TAOS_1
TAOS_2
TAOS_3
128
103
102
69
70
71
72
TYPE
I
I
DESCRIPTION
Transmitter Clock Input for Channel _0 - Host mode and Hardware mode
E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm.
During normal operation TCLK_0 is used for sampling input data at TPOS_0/
TDATA_0 and TNEG_0/CODES_0 while MCLK is used as the timing refer-
ence for the transmit pulse shaping circuit.
Transmitter Clock Input for Channel _1
Transmitter Clock Input for Channel _2
Transmitter Clock Input for Channel _3
NOTE: Internally pulled “Low” with a 50kresistor for all channels.
Transmit All Ones for Channel _0 - Hardware mode
Setting this pin "High" enables the transmission of an “All Ones” Pattern from
Channel _0. A "Low" level stops the transmission of the “All Ones” Pattern.
Transmit All Ones for Channel _1
Transmit All Ones for Channel _2
Transmit All Ones for Channel _3
WR_R/W
RD_DS
ALE_AS
CS
TXON_0
69
70
71
72
122
TXON_1
TXON_2
TXON_3
123
124
125
Host mode: these pins act as various microprocessor functions. See “Micro-
processor Interface” on page 9.
NOTE: These pins are internally pulled “Low” with a 50kresistor.
I Transmitter Turn On for Channel _0
Hardware mode
Setting this pin "High" turns on the Transmit Section of Channel _0 and has no
control of the Channel_0 receiver. When TXON_0 = “0” then TTIP_0 and
TRING_0 driver outputs will be tri-stated.
NOTE: In Hardware mode only, all receiver channels will be turned on upon
power-up and there is no provision to power them off. The receive
channels can only be independently powered on or off in Host mode.
In Host mode
The TXON_n bits in the channel control registers turn each channel Transmit
section ON or OFF. However, control of the on/off function can be transferred
to the Hardware pins by setting the TXONCTL bit (bit 6) to “1” in the register at
address hex 0x42.
Transmitter Turn On for Channel _1
Transmitter Turn On for Channel _2
Transmitter Turn On for Channel _3
NOTE: Internally pulled "Low" with a 50kresistor for all channels.
8

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