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PDF XRT83L314 Data sheet ( Hoja de datos )

Número de pieza XRT83L314
Descripción 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
Fabricantes Exar Corporation 
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XRT83L314
MAY 2004
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83L314 is a fully integrated 14-channel long-
haul and short-haul line interface unit (LIU) that
operates from a single 3.3V power supply. Using
internal termination, the LIU provides one bill of
materials to operate in T1, E1, or J1 mode
independently on a per channel basis with minimum
external components. The LIU features are
programmed through a standard microprocessor
interface. EXAR’s LIU has patented high impedance
circuits that allow the transmitter outputs and receiver
inputs to be high impedance when experiencing a
power failure or when the LIU is powered off. Key
design features within the LIU optimize 1:1 or 1+1
redundancy and non-intrusive monitoring applications
to ensure reliability without using relays.
The on-chip clock synthesizer generates T1/E1/J1
clock rates from a selectable external clock frequency
and has five output clock references that can be used
for external timing (8kHz, 1.544Mhz, 2.048Mhz,
nxT1/J1, nxE1).
Additional features include RLOS, a 16-bit LCV
counter for each channel, AIS, QRSS generation/
detection, Network Loop Code generation/detection,
TAOS, DMO, and diagnostic loopback modes.
APPLICATIONS
T1 Digital Cross Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public Switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Integrated Multi-Service Access Platforms (IMAPs)
Integrated Access Devices (IADs)
Inverse Multiplexing for ATM (IMA)
Wireless Base Stations
FIGURE 1. BLOCK DIAGRAM OF THE XRT83L314
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
ICT
TEST
TxON
1 of 14 Channels
NLCD
Generation
Driver
Monitor
HDB3/B8ZS
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse
Shaper &
Pattern Gen
Remote
Loopback
Digital
Loopback
QRSS
Generation
& Detection
Line
Driver
Analog
Loopback
HDB3/B8ZS
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
NLCD
Detection
AIS & LOS
Detector
Peak
Detector
& Slicer
Rx
Equalizer
Rx Equalizer
Control
Test
Microprocessor
Interface
Programmable Master
Clock Synthesizer
TTIP
TRING
RTIP
RRING
DMO
RLOS
8kHzOUT
MCLKE1out
MCLKT1out
MCLKE1Nout
MCLKT1Nout
RxON
RxTSEL
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XRT83L314 pdf
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
FIGURE 17. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 25
2.10 RXMUTE (RECEIVER LOS WITH DATA MUTING) ..................................................................................... 25
FIGURE 18. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION................................................................................................... 25
3.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 26
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 26
3.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 26
FIGURE 20. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK...................................................................................................... 26
FIGURE 21. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK........................................................................................................ 26
3.2 HDB3/B8ZS ENCODER .................................................................................................................................. 27
TABLE 7: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 27
TABLE 8: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 27
TABLE 9: EXAMPLES OF B8ZS ENCODING............................................................................................................................................. 27
3.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 28
3.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 28
FIGURE 22. TAOS (TRANSMIT ALL ONES) ............................................................................................................................................ 28
3.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 28
TABLE 10: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS......................................................................................... 28
3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 29
FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION ..................................................................................................... 29
3.5.2 NETWORK LOOP UP CODE...................................................................................................................................... 29
FIGURE 24. NETWORK LOOP UP CODE GENERATION ............................................................................................................................ 29
3.5.3 NETWORK LOOP DOWN CODE ............................................................................................................................... 29
FIGURE 25. NETWORK LOOP DOWN CODE GENERATION ....................................................................................................................... 29
3.5.4 QRSS GENERATION.................................................................................................................................................. 30
3.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 30
3.6.1 T1 LONG HAUL LINE BUILD OUT (LBO).................................................................................................................. 30
FIGURE 26. LONG HAUL LINE BUILD OUT WITH -7.5DB ATTENUATION .................................................................................................... 30
TABLE 11: RANDOM BIT SEQUENCE POLYNOMIALS................................................................................................................................ 30
FIGURE 27. LONG HAUL LINE BUILD OUT WITH -15DB ATTENUATION ..................................................................................................... 31
FIGURE 28. LONG HAUL LINE BUILD OUT WITH -22.5DB ATTENUATION .................................................................................................. 31
3.6.2 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 32
3.6.3 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 32
FIGURE 29. ARBITRARY PULSE SEGMENT ASSIGNMENT ......................................................................................................................... 32
3.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 32
TABLE 12: SHORT HAUL LINE BUILD OUT.............................................................................................................................................. 32
3.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 33
FIGURE 30. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ......................................................................................... 33
4.0 T1/E1 APPLICATIONS ........................................................................................................................ 34
4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 34
4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 34
FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK................................................................................................ 34
4.1.2 REMOTE LOOPBACK ................................................................................................................................................ 34
FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .......................................................................................................... 34
4.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 35
FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ........................................................................................................... 35
4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 35
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ............................................................................................................... 35
4.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 36
FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ........................................................................................... 36
TABLE 13: CHIP SELECT ASSIGNMENTS ................................................................................................................................................ 36
4.3 LINE CARD REDUNDANCY .......................................................................................................................... 37
4.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 37
4.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 37
FIGURE 36. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ................................................ 37
4.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 37
FIGURE 37. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY.................................................. 38
4.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 38
4.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 39
FIGURE 38. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ............................................................ 39
4.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 40
FIGURE 39. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY .............................................................. 40
4.4 POWER FAILURE PROTECTION .................................................................................................................. 41
4.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 41
4.6 NON-INTRUSIVE MONITORING .................................................................................................................... 41
II

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XRT83L314 arduino
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
TRANSMITTER SECTION
NAME
PIN
TxON
AC20
TYPE
I
DMO
Y4 O
TCLK13
TCLK12
TCLK11
TCLK10
TCLK9
TCLK8
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
TPOS13
TPOS12
TPOS11
TPOS10
TPOS9
TPOS8
TPOS7
TPOS6
TPOS5
TPOS4
TPOS3
TPOS2
TPOS1
TPOS0
Y16
Y17
AC18
D16
C17
A19
B16
D7
A3
B5
B6
AC6
AC5
AC7
AB17
AA18
AB18
A18
D17
B19
A17
B7
C4
B4
D6
AB6
AA6
Y8
I
I
DESCRIPTION
Transmit On/Off Input
Upon power up, the transmitters are powered off. Turning the transmitters On
or Off is selected through the microprocessor interface by programming the
appropriate channel register if this pin is pulled "High". If the TxON pin is
pulled "Low", all 14 transmitters are powered off.
NOTE: TxON is ideal for redundancy applications. See the Redundancy
Applications Section of this datasheet for more details. Internally
pulled "Low" with a 50Kresistor.
Digital Monitor Output (Global Pin for All 14-Channels)
When no transmit output pulse is detected for more than 128 TCLK cycles on
one of the 14-channels, the DMO pin will go "High" for a minimum of one TCLK
cycle. DMO will remain "High" until the transmitter sends a valid pulse.
NOTE: This pin is for redundancy applications to initiate an automatic switch to
the backup card. For individual channel DMO, see the register map.
Transmit Clock Input
TCLK is the input facility clock used to sample the incoming TPOS/TNEG data.
If TCLK is absent, pulled "Low", or pulled "High", the transmitter outputs at
TTIP/TRING can be selected to send an all ones or an all zero signal by pro-
gramming TCLKCNL in the appropriate global register. TPOS/TNEG data can
be sampled on either edge of TCLK selected by TCLKE in the appropriate glo-
bal register.
NOTE: TCLKE is a global setting that applies to all 14 channels.
TPOS/TDATA Input
Transmit digital input pin. In dual rail mode, this pin is the transmit positive
data input. In single rail mode, this pin is the transmit non-return to zero (NRZ)
data input.
NOTE: Internally pulled "Low" with a 50Kresistor.
7

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