PDF XRT79L74 Data sheet ( Hoja de datos )

Número de pieza	XRT79L74
Descripción	4-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
Fabricantes	Exar Corporation
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No Preview Available ! www.DataSheet4U.com PRELIMINARY XRT79L74 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC MARCH 2004 REGISTER MANUAL The XRT79L74 is a four channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing. For ATM UNI applications, this device provides the ATM Physical Layer (Physi- cal Medium Dependent and Transmission Conver- gence sub-layers) interface for the public and private networks at DS3/E3 rates. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload. The XRT79L74 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of ATM or HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control. Industry standard UTOPIA II and POS-PHY interface are also provided. GENERAL FEATURES: • Integrated T3/E3 Line Interface Unit • Integrated Jitter Attenuator that can be selected either in Receive or Transmit path • Flexible integrated Clock Multiplier that takes single frequency clock and generates either DS3 or E3 frequency. • 8/16 bit UTOPIA Level I and II and PPP Multi-PHY Interface operating at 25, 33 or 50 MHz. • HDLC Controller that provides the mapping/ extraction of either bit or byte mapped encapsulated packet from DS3/E3 Frame. • Contains on-chip 16 cell FIFO (configurable in depths of 4, 8, 12 or 16 cells), in both the Transmit (TxFIFO) and Receive Directions (RxFIFO) • Contains on-chip 54 byte Transmit and Receive OAM Cell Buffer for transmission, reception and processing of OAM Cells • Supports ATM cell or PPP Packet Mapping • Supports M13 and C-Bit Parity Framing Formats • Supports DS3/E3 Clear-Channel Framing. • Includes PRBS Generator and Receiver • Supports Line, Cell, and PLCP Loop-backs • Interfaces to 8 Bit wide Intel, Motorola or PowerPC • Low power 3.3V, 5V Input Tolerant, CMOS • Available in 456 Lead PBGA Package • JTAG Interface LINE INTERFACE UNIT REV. P1.0.0 • On chip Clock and Data Recovery circuit for high input jitter tolerance • Meets E3/DS3 Jitter Tolerance Requirements • Detects and Clears LOS as per G.775. • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation • Compliant with jitter transfer template outlined in ITU G.751, G.752, G.755 and GR-499-CORE,1995 standards • Meets ETSI TBR 24 and GR-499 Jitter Transfer Requirements • On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled • On-chip clock synthesizer provides the appropriate rate clock from a single 12.288 MHz Clock • On chip advanced crystal-less Jitter Attenuator • Jitter Attenuator can be selected in Receive or Transmit paths • 16 or 32 bits selectable FIFO size • Meets the Jitter and Wander specifications described in T1.105.03b,ETSI TBR-24, Bellcore GR-253 and GR-499 standards • Jitter Attenuator can be disabled • Maximum power consumption 3.1W DS3/E3 FRAMER • DS3 framer supports both M13 and C-bit parity. • DS3 framer meets ANSI T1.107 and T1.404 standards. • Detects OOF,LOF,AIS,RDI/FERF alarms. • Generation and Insertion of FEBE on received parity errors supported. • Automatic insertion of RDI/FERF on alarm status. • E3 framer meets G.832,G.751 standards. • Framers can be bypassed. ATM/PPP PROTOCOL PROCESSOR TRANSMIT CELL PROCESSING • Extracts ATM cells • Supports ATM cell payload scrambling • Maps ATM cells into E3 or DS3 frame • PLCP frame and mapping of ATM cell streams RECEIVE CELL PROCESSING Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page PRELIMINARY 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC XRT79L74 REV. P1.0.0 LIU ALARM STATUS REGISTER (ADDRESS = 0XN303)................................................................................... 42 LIU TRANSMIT CONTROL REGISTER (ADDRESS = 0XN304) ........................................................................... 45 LIU RECEIVE CONTROL REGISTER (ADDRESS = 0XN305) ............................................................................. 47 LIU CHANNEL CONTROL REGISTER (ADDRESS = 0XN306) ............................................................................ 49 JITTER ATTENUATOR CONTROL REGISTER (ADDRESS = 0XN307) .................................................................. 50 LIU RECEIVE APS/REDUNDANCY CONTROL REGISTER (ADDRESS = 0XN308) ............................................... 51 ORDERING INFORMATION ............................................................................................ 52 PACKAGE DIMENSIONS ................................................................................................ 52 REVISION HISTORY ...................................................................................................................................... 53 B 5 Page PRELIMINARY 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC XRT79L74 REV. P1.0.0 CLEAR-CHANNEL FRAMER BLOCK REGISTERS ADDRESS LOCATION REGISTER NAME TYPE DEFAULT VALUE CHANNEL CONTROL REGISTERS (N = CHANNEL NUMBER) CLEAR-CHANNEL FRAMER BLOCK REGISTERS 0xn170 One Second Accumulator - P-Bit/BIP-8/BIP-4 Error Count Register - MSB R/O 0x00 0xn171 One Second Accumulator - P-Bit/BIP-8/BIP-4 Error Count Register - LSB R/O 0x00 0xn172 One Second Accumulator - CP Bit Error Count Register - MSB R/O 0x00 0xn173 One Second Accumulator - CP Bit Error Count Register - LSB R/O 0x00 0xn174 - 0xn17F Reserved 0xn180 Line Interface Drive Register R/W 0x08 0xn181 Line Interface Scan Register R/O 0x00 0xn182 Reserved R/O 0x00 0xn183 Transmit LAPD Byte Count Register R/W 0x00 0xn184 Receive LAPD Byte Count Register R/W 0x00 0xn185 - 0xn18F Reserved R/O 0x00 0xn190 RxPLCP Configuration & Status Register R/O & R/ W 0x06 0xn191 RxPLCP Interrupt Enable Register R/W 0x00 0xn192 RxPLCP Interrupt Status Register RUR 0x00 0xn193 - 0xn197 Reserved 0xn198 TxPLCP A1 Byte Error Mask Register R/W 0x00 0xn199 TxPLCP A2 Byte Error Mask Register R/W 0x00 0xn19A TxPLCP BIP-8 Byte Error Mask Register R/W 0x00 0xn19B TxPLCP G1 Byte Register R/W 0x00 0xn19C - 0xn2FF Reserved LIU/JITTER ATTENUATOR CONTROL REGISTERS ADDRESS LOCATION REGISTER NAME 0xn300 0xn301 0xn302 0xn303 CHANNEL CONTROL REGISTERS (N = CHANNEL NUMBER) LIU/JITTER ATTENUATOR CONTROL REGISTERS LIU Transmit APS/Redundancy Control Register LIU Interrupt Enable Register LIU Interrupt Status Register LIU Alarm Status Register TYPE DEFAULT VALUE R/W R/W RUR R/O 0x00 0x00 0x00 0x00 9 11 Page

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