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PDF XRT75R03D Data sheet ( Hoja de datos )
| Número de pieza | XRT75R03D | |
| Descripción | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75R03D
EXAR DATA SHEET FORMAT TEMPLATES
MARCH 2006
REV. 1.0.4
GENERAL DESCRIPTION
The XRT75R03D is a three-channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R3
Technology (Reconfigurable, Relayless Redundancy)
with Jitter Attenuator for E3/DS3/STS-1 applications.
It incorporates 3 independent Receivers,
Transmitters and Jitter Attenuators in a single 128 pin
LQFP package.
Each channel of the XRT75R03D can be
independently configured to operate in the data rate,
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz). Each transmitter can be turned off and tri-
stated for redundancy support or for conserving
power.
The XRT75R03D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75R03D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75R03D provides both Serial
Microprocessor Interface as well as Hardware mode
for programming and control.
The XRT75R03D supports local, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
FEATURES
RECEIVER:
• R3 Technology (Reconfigurable, Relayless
Redundancy)
• On chip Clock and Data Recovery circuit for high
input jitter tolerance
• Meets E3/DS3/STS-1 Jitter Tolerance Requirement
• Detects and Clears LOS as per G.775
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
• Provides low jitter output clock
TRANSMITTER:
• R3 Technology (Reconfigurable, Relayless
Redundancy)
• Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Each Transmitter can be independently turned on
or off
• Transmitters provide Voltage Output Drive
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator for
each channel
• Jitter Attenuator can be selected in Receive or
Transmit paths
• Meets ETSI TBR 24 Jitter Transfer Requirements
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
• Jitter Attenuator can be disabled
CONTROL AND DIAGNOSTICS:
• 5 wire Serial Microprocessor Interface for control
and configuration
• Supports optional internal Transmit driver
monitoring
• Hardware Mode for control and configuration
• Each channel supports Local, Remote and Digital
Loop-backs
• Single 3.3 V ± 5% power supply
• 5 V Tolerant I/O
• Available in 128 pin LQFP
• - 40°C to 85°C Industrial Temperature Range
APPLICATIONS
• E3/DS3 Access Equipment
• STS1-SPE to DS3 De-Synchronizing
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT75R03D
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
6.0 THE RECEIVER SECTION: ................................................................................................................. 44
6.1 AGC/EQUALIZER: .......................................................................................................................................... 44
6.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 45
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 45
FIGURE 19. INTERFERENCE MARGIN TEST SET UP FOR E3. ............................................................................................................ 46
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 46
6.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 46
6.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 47
6.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 47
6.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 47
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3
AND STS-1 APPLICATIONS)............................................................................................................................................. 47
DISABLING ALOS/DLOS DETECTION: .......................................................................................................... 47
6.4.2 E3 LOS CONDITION:.................................................................................................................................................. 47
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.......................................................................................... 48
FIGURE 21. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 48
6.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 49
7.0 JITTER: ................................................................................................................................................ 49
7.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 49
FIGURE 22. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 49
7.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 49
FIGURE 23. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 50
7.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 50
FIGURE 24. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 50
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................. 51
7.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 51
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................................................ 51
7.3 JITTER ATTENUATOR: ................................................................................................................................. 51
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 52
FIGURE 25. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 52
7.3.1 JITTER GENERATION: .............................................................................................................................................. 52
8.0 SERIAL HOST INTERFACE: ............................................................................................................... 52
TABLE 14: FUNCTIONS OF SHARED PINS ......................................................................................................................................... 53
TABLE 15: XRT75R03D REGISTER MAP - QUICK LOOK ................................................................................................................. 54
Legend: ..................................................................................................................................................................... 57
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU IC57
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
57
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................ 59
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS ................................................................................................. 59
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................... 59
TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ............................................................... 59
TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20)....................................................... 62
TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21)....................................................... 63
TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E) ....................................................................... 64
TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F)..................................................................... 65
THE PER-CHANNEL REGISTERS ........................................................................................................... 65
TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
65
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................... 67
TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 .............................................. 67
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 .............................................. 69
TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03............................................................................. 71
TABLE 27: TRANSMIT CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X04 ..................................................................... 76
TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05 ....................................................................... 79
TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ...................................................................... 81
TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ..................................................... 84
9.0 DIAGNOSTIC FEATURES: ................................................................................................................. 86
9.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 86
FIGURE 26. PRBS MODE ............................................................................................................................................................. 86
9.2 LOOPBACKS: ................................................................................................................................................ 86
9.2.1 ANALOG LOOPBACK:............................................................................................................................................... 86
FIGURE 27. ANALOG LOOPBACK..................................................................................................................................................... 87
II
5 Page 
XRT75R03D
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
40 DMO_0
127 DMO_1
22 DMO_2
O Drive Monitor Output - Channel 0:
Drive Monitor Output - Channel 1:
Drive Monitor Output - Channel 2:
These output signals are used to indicate some sort of fault condition within
the Transmit Output signal path.
This output pin will toggle "High" anytime the Transmit Drive Monitor cir-
cuitry either, via the corresponding MTIP and MRING input pins or inter-
nally, detects no bipolar pulses via the Transmit Output line signal (e.g., via
the TTIP_n and TRING_n output pins) for 128 bit-periods.
This output pin will be driven "Low" anytime the Transmit Drive Monitor cir-
cuitry has detected at least one bipolar pulse via the Transmit Output line
signal within the last 128 bit periods.
67 TxClkINV/
SClk
I Hardware Mode: Transmit Clock Invert
Host Mode: Serial Clock Input:
Hardware mode
This input pin is used to select the edge of the TxCLK_n input that the
Transmit Section of all channels will use to sample the TPDATA_n and
TNDATA_n input pins.
Setting this input pin “High” configures all three Transmitters to sample the
TPData_n and TNData_n data on the rising edge of the TxClk_n .
Setting this input pin “Low” configures all three Transmitters to sample the
TPData_n and TNData_n data on the falling edge of the TxClk_n .
Host Mode
In the Host Mode this pin functions as SClk input pin please refer to the pin
descriptions for the Microprocessor interface.
7
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