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PDF XRT75L04D Data sheet ( Hoja de datos )
| Número de pieza | XRT75L04D | |
| Descripción | FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75L04D
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NOVEMBER 2003
GENERAL DESCRIPTION
The XRT75L04D is a four-channel fully integrated
Line Interface Unit (LIU) with Sonet Desynchronizer
for E3/DS3/STS-1 applications. It incorporates four
independent Receivers, Transmitters and Jitter
Attenuators in a single 176 pin QFP package.
Each channel of the XRT75L04D can be configured
to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or
STS-1 (51.84 MHz) rates that are independent of
each other. Each transmitter can be turned off and tri-
stated for redundancy support and for conserving
power.
The XRT75L04D’s differential receivers provide high
noise interference margin and are able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L04D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Telcordia GR-499, GR-253 specifications. Also, the
jitter attenuator can be used for clock smoothing in
SONET STS-1 to DS3 de-mapping.
The XRT75L04D provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L04D supports local, remote and digital
loop-backs. The XRT75L04D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance.
• Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
• On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
• On-chip clock synthesizer generates the
appropriate rate clock from a single frequency
XTAL.
REV. 1.0.1
• Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
TRANSMITTER:
• Compliant with Telcordia GR-499, GR-253 and
ANSI T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Transmitters can be turned on or off.
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator.
• Jitter Attenuators can be selected in Receive or
Transmit paths.
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-253 and GR-499-
CORE,1995 standards.
• Meets ETSI TBR 24 Jitter Transfer Requirements.
• 16 ,32 or 128 bits selectable FIFO size.
• Meets the Wander specifications described in
T1.105.03b.
• Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
• Serial Microprocessor Interface for control and
configuration.
• Supports optional internal Transmit Driver
Monitoring.
• PRBS error counter register to accumulate errors.
• Supports Local, Remote and Digital Loop-backs.
• Single 3.3 V ± 5% power supply.
• 5 V Tolerant I/O.
• Maximum Power Dissipation 1.8W.
• Available in 176 pin QFP package
• - 40°C to 85°C Industrial Temperature Range.
APPLICATIONS
• E3/DS3 Access Equipment.
• STS1-SPE to DS3 Mapper.
• DSLAMs.
• Digital Cross Connect Systems.
• CSU/DSU Equipment.
• Routers.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT75L04D
REV. 1.0.1 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
5.1 AGC/EQUALIZER: .......................................................................................................................................... 30
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 30
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1 ...................................................................................................... 30
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 31
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 31
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3. ................................................................................................................... 31
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ................................................................................................................................. 31
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 32
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 32
DISABLING ALOS/DLOS DETECTION: .......................................................................................................................... 32
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 32
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1 AP-
PLICATIONS).......................................................................................................................................................................... 32
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 ................................................................................................ 33
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775................................................................................................. 33
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 34
6.0 JITTER: ................................................................................................................................................ 35
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 35
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 35
FIGURE 21. JITTER TOLERANCE MEASUREMENTS .................................................................................................................................. 35
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 36
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1 ...................................................................................................................... 36
FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .................................................................................................................................... 36
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 37
6.3 JITTER GENERATION: .................................................................................................................................. 37
6.4 JITTER ATTENUATOR: ................................................................................................................................. 37
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ......................................................................... 37
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................................................... 37
TABLE 13: JITTER TRANSFER PASS MASKS........................................................................................................................................... 38
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE ...................................................................... 38
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 39
TABLE 14: FUNCTIONS OF SHARED PINS................................................................................................................................................ 39
TABLE 15: REGISTER MAP AND BIT NAMES ........................................................................................................................................... 39
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................................................... 40
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS .................................................................................................... 41
TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS .................................................................................................... 41
TABLE 19: REGISTER MAP AND BIT NAMES - CHANNEL 2 REGISTERS .................................................................................................... 42
TABLE 20: REGISTER MAP AND BIT NAMES - CHANNEL 3 REGISTERS .................................................................................................... 42
TABLE 21: REGISTER MAP DESCRIPTION .............................................................................................................................................. 43
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 47
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 47
8.2 LOOPBACKS: ................................................................................................................................................ 48
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 48
FIGURE 25. PRBS MODE ................................................................................................................................................................... 48
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 49
FIGURE 26. ANALOG LOOPBACK ........................................................................................................................................................... 49
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 50
FIGURE 27. DIGITAL LOOPBACK ............................................................................................................................................................ 50
FIGURE 28. REMOTE LOOPBACK ........................................................................................................................................................... 50
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 51
FIGURE 29. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 51
9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ............................................................... 52
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 52
FIGURE 30. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ............... 53
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 54
9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 54
9.2.1.1 A BRIEF DESCRIPTION OF AN STS-1 FRAME ......................................................................................................... 54
FIGURE 31. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME ..................................................................................................... 55
FIGURE 32. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
56
FIGURE 33. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 57
FIGURE 34. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 58
9.2.1.2 MAPPING DS3 DATA INTO AN STS-1 SPE ............................................................................................................ 59
FIGURE 35. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE ............................................................................................. 59
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XRT75L04D
REV. 1.0.1 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
RECEIVE INTERFACE
PIN #
SIGNAL NAME
78 RxCLK_0
71 RXCLK_1
143 RxCLK_2
150 RxCLK_3
80 RPOS_0
73 RPOS_1
141 RPOS_2
148 RPOS_3
79 RNEG_0/LCV_0
72 RNEG_1/LCV_1
142 RNEG_2/LCV_2
149 RNEG_3/LCV_3
97 RRING_0
106 RRING_1
124 RRING_2
115 RRING_3
98 RTIP_0
107 RTIP_1
123 RTIP_2
114 RTIP_3
TYPE
O
O
O
I
I
DESCRIPTION
Receive Clock Output - Channel 0:
Receive Clock Output - Channel 1:
Receive Clock Output - Channel 2:
Receive Clock Output - Channel 3:
By default, RPOS and RNEG data sampled on the rising edge RxCLK..
Set the RxCLKINV bit to sample RPOS/RNEG data on the falling edge of
RxCLK
Receive Positive Data Output - Channel 0:
Receive Positive Data Output - Channel 1:
Receive Positive Data Output - Channel 2:
Receive Positive Data Output - Channel 3:
NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero
suppression patterns in the incoming line signal (such as: "00V",
"000V", "B0V", "B00V") is removed and replaced with ‘0’.
Receive Negative Data Output/Line Code Violation Indicator -
Channel 0:
Receive Negative Data Output/Line Code Violation Indicator -
Channel 1:
Receive Negative Data Output/Line Code Violation Indicator -
Channel 2:
Receive Negative Data Output/Line Code Violation Indicator -
Channel 3:
In Dual Rail mode, a negative pulse is output through RNEG.
Line Code Violation Indicator - Channel n:
If configured in Single Rail mode then Line Code Violation will be output.
Receive Ring Input - Channel 0:
Receive Ring Input - Channel 1:
Receive Ring Input - Channel 2:
Receive Ring Input - Channel 3:
These pins along with RTIP receive the bipolar line signal from the remote DS3/
E3/STS-1 Terminal.
Receive TIP Input - Channel 0:
Receive TIP Input - Channel 1:
Receive TIP Input - Channel 2:
Receive TIP Input - Channel 3:
These pins along with RRING receive the bipolar line signal from the Remote
DS3/E3/STS-1 Terminal.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT75L04D.PDF ] | |
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