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PDF XRT75L03D Data sheet ( Hoja de datos )
| Número de pieza | XRT75L03D | |
| Descripción | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
JUNE 2003
GENERAL DESCRIPTION
The XRT75L03D is a three-channel fully integrated
Line Interface Unit (LIU) with Jitter Attenuator for E3/
DS3/STS-1 applications. It incorporates 3
independent Receivers, Transmitters and Jitter
Attenuators in a single 128 pin LQFP package.
Each channel of the XRT75L03D can be
independently configured to operate in the data rate,
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz). Each transmitter can be turned off and tri-
stated for redundancy support or for conserving
power.
The XRT75L03D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L03D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75L03D provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L03D supports local, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
FEATURES
TRANSMITTER:
REV. 1.0.0
• Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Each Transmitter can be turned on or off
• Transmitters provide Current Drive Output
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator for
each channel
• Jitter Attenuator can be selected in Receive or
Transmit paths
• Meets ETSI TBR 24 Jitter Transfer Requirements
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
• Jitter Attenuator can be disabled
CONTROL AND DIAGNOSTICS:
• 5 wire Serial Microprocessor Interface for control
and configuration
• Supports optional internal Transmit driver
monitoring
• Hardware Mode for control and configuration
• Each channel supports Local, Remote and Digital
Loop-backs
• Single 3.3 V ± 5% power supply
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance
• Meets E3/DS3/STS-1 Jitter Tolerance Requirement
• Detects and Clears LOS as per G.775
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
• Provides low jitter output clock
• 5 V Tolerant I/O
• Available in 128 pin Thermally enhanced LQFP
Package
• - 40°C to 85°C Industrial Temperature Range
APPLICATIONS
• E3/DS3 Access Equipment
• STS1-SPE to DS3 De-Synchronizing
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
5.1 AGC/EQUALIZER: ............................................................................................................................................ 44
Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 44
5.1.1 Interference Tolerance: ..................................................................................................................... 45
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 45
5.2 CLOCK AND DATA RECOVERY: ......................................................................................................................... 46
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 46
TABLE 9: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 46
5.3 B3ZS/HDB3 DECODER: .................................................................................................................................. 47
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ................................................................................................................ 47
5.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 47
DISABLING ALOS/DLOS DETECTION: ......................................................................................................... 47
5.4.2 E3 LOS Condition: ............................................................................................................................. 47
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 47
Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 48
Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 48
5.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 49
6.0 Jitter: ................................................................................................................................................. 49
6.1 JITTER TOLERANCE - RECEIVER: ...................................................................................................................... 49
6.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 49
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 49
6.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 50
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 50
Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 50
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: .................................................................................................. 51
6.3 JITTER ATTENUATOR: ...................................................................................................................................... 51
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ..................................... 51
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................... 51
6.3.1 Jitter Generation: ............................................................................................................................... 52
7.0 Serial Host interface: ....................................................................................................................... 52
TABLE 13: JITTER TRANSFER PASS MASKS ....................................................................................................... 52
Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 52
TABLE 14: FUNCTIONS OF SHARED PINS ............................................................................................................ 53
TABLE 15: XRT75L03D REGISTER MAP - QUICK LOOK ..................................................................................... 54
................................................................................................................................................................. 56
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU IC ..
56
Legend: ..................................................................................................................................................................56
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER
ATTENUATOR IC ................................................................................................................................. 56
THE GLOBAL/CHIP-LEVEL REGISTERS ............................................................................................... 58
................................................................................................................................................................. 58
REGISTER DESCRIPTION - GLOBAL REGISTERS .............................................................................. 58
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS .................................................................... 58
TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) .................................. 58
TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20) ......................... 61
TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21) ......................... 62
TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E) .......................................... 63
................................................................................................................................................................. 64
THE PER-CHANNEL REGISTERS ......................................................................................................... 64
TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F) ........................................ 64
TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER
ATTENUATOR IC ................................................................................................................................. 64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS ................................................................... 66
TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 ................. 66
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 ................. 68
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
37 TAOS_0
7 TAOS_1
8 TAOS_2
I Transmit "All Ones" Input - Channel 0:
Transmit "All Ones" Input - Channel 1:
Transmit "All Ones" Input - Channel 2:
These input pin are used to configure the Transmit Section of the corre-
sponding channel to generate and transmit an unframed "All Ones" pattern
via the DS3, E3 or STS-1 line signal to the remote terminal equipment.
When this configuration is implemented the Transmit Section will ignore the
data that it is accepting from the System-side equipment and will overwrite
this data will the "All Ones" Pattern.
"Low" - Does not configure the channel to transmit an unframed "All Ones"
Pattern to the remote terminal equipment. In this mode, the Transmit Sec-
tion of the Channel will output data based upon the signals that are applied
to the TxPOS_n and TxNEG_n input pins.
"High" - Configures the Channel to transmit an unframed "All Ones" Pattern
to the remote terminal equipment. In this mode, the Transmit Section will
override the data that is applied to the TxPOS_n and TxNEG_n input pins,
and will proceed to generate and transmit an unframed "All Ones" pattern.
4. This input pin is ignored if the XRT75L03D is operating in the
HOST Mode and should be tied to GND.
5. These input pins are internally pulled down.
36 TxLEV_0
9 TxLEV_1
10 TxLEV_2
I Transmit Line Build-Out Enable/Disable Select - Channel 0:
Transmit Line Build-Out Enable/Disable Select - Channel 1:
Transmit Line Build-Out Enable/Disable Select - Channel 2:
These input pins are used to enable or disable the Transmit Line Build-Out
(e.g., pulse-shaping) circuit within the corresponding channel. The user
should set these input pins either "High" or "Low" based upon the following
guidelines.
"Low" - If the cable length between the Transmit Output of the correspond-
ing Channel and the DSX-3/STSX-1 location is 225 feet or less.
"High" - If the cable length between the Transmit Output of the correspond-
ing Channel and the DSX-3/STSX-1 location is 225 feet or more.
NOTES:
1. These guidelines must be followed in order to insure that the
Transmit Section of Channel_n will always generate a DS3 pulse
that complies with the Isolated Pulse Template requirements per
Bellcore GR-499-CORE, or an STS-1 pulse that complies with the
Pulse Template requirements per Telcordia GR-253-CORE.
2. This input pin is inactive if the XRT75L03D has been configured to
operate in the Host Mode, or if the corresponding channel has
been configured to operate in the E3 Mode. If either of these
cases are true, then tie this input pin to GND.
3. These input pins are internally pulled "Low".
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