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PDF XRT75L02 Data sheet ( Hoja de datos )
| Número de pieza | XRT75L02 | |
| Descripción | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
DECEMBER 2005
GENERAL DESCRIPTION
The XRT75L02 is a two-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates independent
Receivers, Transmitters and Jitter Attenuators in a
single 100 pin TQFP package.
The XRT75L02 can be configured to operate in either
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz) modes.The transmitter can be turned off (tri-
stated) for redundancy support and for conserving
power.
The XRT75L02’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L02 incorporates advanced crystal-less
jitter attenuators that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications.
The XRT75L02 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L02 supports local,remote and digital
loop-backs. The XRT75L02 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance.
• Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
• On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
• On-chip clock synthesizer generates the
appropriate rate clock from a single frequency
XTAL.
REV. 1.0.3
• Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
• Provides low jitter output clock.
TRANSMITTER:
• Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Transmitters can be turned on or off.
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator.
• Jitter Attenuator can be selected in Receive or
Transmit paths.
• 16 or 32 bits selectable FIFO size.
• Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
• Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
• 5 wire Serial Microprocessor Interface for control
and configuration.
• Supports optional internal Transmit Driver
Monitoring.
• PRBS error counter register to accumulate errors.
• Hardware Mode for control and configuration.
• Supports Local, Remote and Digital Loop-backs.
• Single 3.3 V ± 5% power supply.
• 5 V Tolerant I/O.
• Available in 100 pin TQFP.
• -40°C to 85°C Industrial Temperature Range.
APPLICATIONS
• E3/DS3 Access Equipment.
• STS1-SPE to DS3 Mapper.
• DSLAMs.
• Digital Cross Connect Systems.
• CSU/DSU Equipment.
• Routers.
• Fiber Optic Terminals.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 28
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 28
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.............................................................................................................. 28
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 28
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................. 29
5.4 LOS (LOSS OF SIGNAL) DETECTOR: .......................................................................................................... 29
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 29
DISABLING ALOS/DLOS DETECTION:...........................................................................................................29
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 29
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1
APPLICATIONS) ............................................................................................................................................................... 29
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION: ................................................................................... 30
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 .......................................................................................... 30
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 30
6.0 JITTER: ................................................................................................................................................31
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 31
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS: ............................................................................................... 31
FIGURE 21. JITTER TOLERANCE MEASUREMENTS............................................................................................................................ 31
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 32
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1 ................................................................................................................ 32
FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 32
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 33
6.3 JITTER GENERATION: .................................................................................................................................. 33
6.4 JITTER ATTENUATOR: ................................................................................................................................. 33
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)................................................................... 33
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES............................................................................................................. 33
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 34
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 34
7.0 SERIAL HOST INTERFACE: ...............................................................................................................35
TABLE 14: FUNCTIONS OF SHARED PINS ......................................................................................................................................... 35
TABLE 15: REGISTER MAP AND BIT NAMES .................................................................................................................................... 35
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL......................................................................................................................... 36
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS.............................................................................................. 36
TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS.............................................................................................. 37
TABLE 19: REGISTER MAP DESCRIPTION - CHANNEL 0.................................................................................................................... 38
8.0 DIAGNOSTIC FEATURES: ..................................................................................................................42
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 42
8.2 LOOPBACKS: ................................................................................................................................................. 42
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 42
FIGURE 25. PRBS MODE ............................................................................................................................................................. 42
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 43
8.2.3 IREMOTE LOOPBACK:.............................................................................................................................................. 43
FIGURE 26. ANALOG LOOPBACK ..................................................................................................................................................... 43
FIGURE 27. DIGITAL LOOPBACK...................................................................................................................................................... 43
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 44
FIGURE 28. REMOTE LOOPBACK .................................................................................................................................................... 44
FIGURE 29. TRANSMIT ALL ONES (TAOS) ...................................................................................................................................... 44
TABLE 20: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 45
TABLE 21: TRANSFORMER DETAILS ................................................................................................................................................ 45
ORDERING INFORMATION.............................................................................................47
PACKAGE DIMENSIONS.................................................................................................47
REVISION HISTORY.......................................................................................................................................48
II
5 Page 
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
CONTROL AND ALARM INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
73 MRING_0
53 MRING_1
I Monitor Ring Input - Channel 0:
Monitor Ring Input - Channel 1:
The bipolar line output signal from TRING_n is connected to this pin via a 270 Ω
resistor to check for line driver failure.
NOTE: This pin is internally pulled "High".
72 MTIP_0
54 MTIP_1
I Monitor Tip Input - Channel 0:
Monitor Tip Input - Channel 1:
The bipolar line output signal from TTIP_n is connected to this pin via a 270-
ohm resistor to check for line driver failure.
NOTE: This pin is internally pulled "High".
79 DMO_0
47 DMO_1
O Drive Monitor Output - Channel 0:
Drive Monitor Output - Channel 1:
If MTIP_n and MRING_n has no transition pulse for 128 ± 32 TxCLK_n cycles,
DMO_n goes “High” to indicate the driver failure. DMO_n output stays “High”
until the next AMI signal is detected.
94 RLOS_0
33 RLOS_1
O Receive Loss of Signal Output Indicator - Channel 0:
Receive Loss of Signal Output Indicator - Channel 1:
This output pin toggles "High" if the receiver has detected a Loss of Signal Con-
dition.
The criteria for declaring /clearing an LOS Condition depends upon whether it is
operating in the E3 or STS-1/DS3 Mode.
95 RLOL_0
32 RLOL_1
O Receive Loss of Lock Output Indicator - Channel 0:
Receive Loss of Lock Output Indicator - Channel 1:
This output pin toggles "High" if a Loss of Lock Condition is detected. LOL
(Loss of Lock) condition occurs if the recovered clock frequency deviates from
the Reference Clock frequency (available at either E3CLK or DS3CLK or STS-
1CLK input pins) by more than 0.5%.
11 RXA
**** External Resistor of 3 K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
12 RXB
**** External Resistor of 3K Ω ±1%.
Should be connected between RxA and RxB for internal bias.
98 ICT
I In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, tie this pin
"High".
NOTE: This pin is internally pulled “High".
96 TEST
**** Factory Test Pin
NOTE: This pin must be connected to GND for normal operation.
9
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| PDF Descargar | [ Datasheet XRT75L02.PDF ] | |
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