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PDF XRT75L00 Data sheet ( Hoja de datos )

Número de pieza XRT75L00
Descripción E3/DS3/STS-1 LINE INTERFACE UNIT
Fabricantes Exar Corporation 
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XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FEBRUARY 2004
GENERAL DESCRIPTION
The XRT75L00 is a single-channel fully integrated
Line Interface Unit (LIU) with Jitter Attenuator for E3/
DS3/STS-1 applications. It incorporates an
independent Receiver, Transmitter and Jitter
Attenuator in a single 52 pin TQFP package.
The XRT75L00 can be configured to operate in either
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz) modes. The transmitter can be turned off (tri-
stated) for redundancy support and for conserving
power.
The XRT75L00’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L00 incorporates an advanced crystal-
less jitter attenuator that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications.
The XRT75L00 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L00 supports local, remote and digital
loop-backs. The XRT75L00 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
REV. 1.0.2
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
Provides low jitter output clock.
TRANSMITTER:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitter can be turned on or off.
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator.
Jitter Attenuator can be selected in Receive or
Transmit paths.
16 or 32 bits selectable FIFO size.
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
Jitter Attenuator can be disabled.
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets E3/DS3/STS-1
Requirements.
Jitter
Tolerance
Detects and Clears LOS as per G.775.
Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
Supports optional internal Transmit Driver
Monitoring.
PRBS error counter register to accumulate errors.
Hardware Mode for control and configuration.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V ± 5% power supply.
5 V Tolerant I/O.
Available in 52 pin TQFP.
-40°C to 85°C Industrial Temperature Range.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards.
Meets ETSI TBR 24 Jitter Transfer Requirements.
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
APPLICATIONS
E3/DS3 Access Equipment.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
Fiber Optic Terminals.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT75L00 pdf
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
5.1 AGC/EQUALIZER ........................................................................................................................................... 28
5.1.1 INTERFERENCE TOLERANCE.................................................................................................................................. 28
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1 ...................................................................................................... 29
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3. ................................................................................................................... 29
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ................................................................................................................................. 29
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 30
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 30
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 30
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 30
DISABLING ALOS/DLOS DETECTOR:........................................................................................................................... 30
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 30
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1 AP-
PLICATIONS).......................................................................................................................................................................... 30
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 ................................................................................................ 31
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775................................................................................................. 31
5.4.2.1 MUTING THE RECOVERED DATA WITH LOS CONDITION: ......................................................................................... 32
6.0 JITTER: ................................................................................................................................................ 33
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 33
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 33
FIGURE 21. JITTER TOLERANCE MEASUREMENTS .................................................................................................................................. 33
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 34
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1 ...................................................................................................................... 34
FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .................................................................................................................................... 34
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 35
6.3 JITTER GENERATION: .................................................................................................................................. 35
6.4 JITTER ATTENUATOR: ................................................................................................................................. 35
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ......................................................................... 35
TABLE 12: JITTER TRANSFER SPECIFICATIONS ...................................................................................................................................... 35
TABLE 13: JITTER TRANSFER PASS MASKS........................................................................................................................................... 36
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE ...................................................................... 36
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 37
TABLE 14: FUNCTIONS OF SHARED PINS................................................................................................................................................ 37
TABLE 15: REGISTER MAP AND BIT NAMES ........................................................................................................................................... 37
TABLE 16: REGISTER MAP DESCRIPTION .............................................................................................................................................. 39
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................................................... 43
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 44
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 44
8.2 LOOPBACKS: ................................................................................................................................................ 44
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 44
FIGURE 25. PRBS MODE ................................................................................................................................................................... 44
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 45
FIGURE 26. ANALOG LOOPBACK ........................................................................................................................................................... 45
FIGURE 27. DIGITAL LOOPBACK ............................................................................................................................................................ 45
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 46
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 46
FIGURE 28. REMOTE LOOPBACK ........................................................................................................................................................... 46
FIGURE 29. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 46
ORDERING INFORMATION ............................................................................................................................................. 47
PACKAGE DIMENSIONS ............................................................................................................. 47
REVISION HISTORY ...................................................................................................................................................... 48
II

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XRT75L00 arduino
REV. 1.0.2
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
OPERATING MODE SELECT
PIN #
21
SIGNAL NAME
HOST/(HW)
TYPE
I
20 E3
I
19 STS-1/DS3
I
22 SR/DR
I
DESCRIPTION
HOST/Hardware Mode Select:
Tie this pin “High” to configure the XRT75L00 in HOST mode. Tie this “Low” to
configure in Hardware mode.
When the XRT75L00 is configured in HOST mode, the states of many discrete
input pins are ignored.
NOTE: This pin is internally pulled up.
E3 Mode Select Input
A "High" on this pin configures to operate in the E3 mode.
A "Low" on this pin configures to operate in either STS-1 or DS3 mode depend-
ing on the setting on pin 19.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and may be tied to GND if the XRT75L00 is
configured to operate in HOST mode.
STS-1/DS3 Select Input
A “High” on this pin configures to operate in STS-1 mode.
A “Low” on this pin configures to operate in DS3 mode.
This pin is ignored if the E3 pin is set to “High”.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and may be tied to GND if the XRT75L00 is
configured to operate in HOST mode.
Single-Rail/Dual-Rail Select:
Setting this “High” configures both the Transmitter and Receiver to operate in
Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In
Single-rail mode, Transmit input at TNData should be grounded.
Setting this “Low” configures both the Transmitter and Receiver to operate in
Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
NOTE: This pin is internally pulled down.
CONTROL AND ALARM INTERFACE
42 MRING
41 MTIP
I Monitor Ring Input
The bipolar line output signal from TRING is connected to this pin via a 270
resistor to check for line driver failure.
NOTE: This pin is internally pulled down.
I Monitor Tip Input
The bipolar line output signal from TTIP is connected to this pin via a 270-ohm
resistor to check for line driver failure.
NOTE: This pin is internally pulled down.
40 DMO
O Drive Monitor Output
If MTIP and MRING has no transition pulse for 128 ± 32 TxClk cycles, DMO
goes “High” to indictae the driver failure. DMO output stays “High” until the next
AMI signal is detected.
9

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