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PDF XRT73LC00A Data sheet ( Hoja de datos )
| Número de pieza | XRT73LC00A | |
| Descripción | E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY XRT73LC00A
AUGUST 2004
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.0
GENERAL DESCRIPTION
The XRT73LC00A DS3/E3/STS-1 Line Interface Unit
is a low power CMOS version of the XRT73L00A and
consists of a line transmitter and receiver integrated
on a single chip and is designed for DS3, E3 or SO-
NET STS-1 applications.
XRT73LC00A can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT73LC00A encodes
input data to either B3ZS (for DS3/STS-1 applica-
tions) or HDB3 (for E3 applications) format and con-
verts the data into the appropriate pulse shapes for
transmission over coaxial cable via a 1:1 transformer.
In the receive direction the XRT73LC00A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of line code violations.
The XRT73LC00A also contains a 4-Wire Micropro-
cessor Serial Interface for accessing the on-chip
Command registers.
FEATURES
• Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L00A
• Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Contains a 4-Wire Microprocessor Serial Interface
• Uses Minimum External components
• Low Power CMOS Design
• Single +3.3V Power Supply
• 5 V Tolerant pins
• -40°C to +85°C Operating Temperature Range
• Available in a 44 pin TQFP package
APPLICATIONS
• Interfaces to E3, DS3 or SONET STS-1 Networks
• CSU/DSU Equipment
• PCM Test Equipment
• Fiber Optic Terminals
• Multiplexers
FIGURE 1. BLOCK DIAGRAM OF THE XRT73LC00A
E3
S TS -1 /D S 3
Ho s t/(H W )
RLOL EXCLK
ICT RCLKINV
RTIP
RRING
RE Q DIS
LOSTHR
SDI
SDO/(LCV)
SClk
CS
REGRESET
TTIP
TRING
MTIP
MRING
DMO
AGC/
Equalizer
Peak
Detector
Slicer
C lo c k
R e c o ve ry
LOS Detector
Serial
Processor
Interface
Loop MUX
Da ta
Recovery
Invert
HDB3/
B3ZS
Decoder
Device
M o n ito r
P u ls e
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Tra n sm it
Logic
Duty Cycle Adjust
RCLK1
LCV/(RCLK2)
RPOS
RNEG
DR/SR
RLOS
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TClk
TXLEV
TXOFF
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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PRELIMINARY
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.0
Figure 28. The Behavior of the RPOS and RCLK1 Output Signals While the XRT73LC00A is Transmitting Sin-
gle-Rail Data to the Receiving Terminal Equipment ..................................................................... 38
4.0 Diagnostic Features of the XRT73LC00A ................................................................ 38
4.1 THE ANALOG LOCAL LOOP-BACK MODE .............................................................................................. 38
Figure 29. The Analog Local Loop-Back in the XRT73LC00A ....................................................................... 39
COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 39
4.2 THE DIGITAL LOCAL LOOP-BACK MODE ............................................................................................... 39
Figure 30. The Digital Local Loop-Back path in the XRT73LC00A ................................................................ 40
COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 40
4.3 THE REMOTE LOOP-BACK MODE ......................................................................................................... 40
Figure 31. The Remote Loop-Back Path in the XRT73LC00A ....................................................................... 41
4.4 TXOFF FEATURES .............................................................................................................................. 41
COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 41
4.5 THE TRANSMIT DRIVE MONITOR FEATURES .......................................................................................... 41
COMMAND REGISTER CR1 (ADDRESS = 0X01) ........................................................................................... 41
Figure 32. The XRT73LC00A Employing the Transmit Drive Monitor Features ............................................. 42
Figure 33. Two LIU’s, Each Monitoring the Transmit Output Signal of the Other LIU IC .............................. 43
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ....................................................................................... 43
COMMAND REGISTER CR1 (ADDRESS = 0X01) ........................................................................................... 43
5.0 The Microprocessor Serial Interface ........................................................................ 44
5.1 DESCRIPTION OF THE COMMAND REGISTERS ........................................................................................ 44
TABLE 5: ADDRESSES AND BIT FORMATS OF XRT73LC00A COMMAND REGISTERS ........................................... 44
DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ..................................................................... 44
5.1.1 Command Register - CR0 ...................................................................................................... 44
5.1.2 Command Register - CR1 ...................................................................................................... 45
5.1.3 Command Register - CR2 ...................................................................................................... 46
5.1.4 Command Register - CR3 ...................................................................................................... 46
5.1.5 Command Register - CR4 ...................................................................................................... 46
5.2 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ...................................................................... 47
TABLE 6: LOOP-BACK MODES ........................................................................................................................... 47
Figure 34. Microprocessor Serial Interface Data Structure ............................................................................ 48
ORDERING INFORMATION ............................................................................................................................ 49
PACKAGE DIMENSIONS ................................................................................................. 49
REVISION HISTORY ..................................................................................................................................... 50
III
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PRELIMINARY
PIN DESCRIPTION
PIN #
30
SYMBOL
LCV/(RCLK2)
31 RCLK1
32 RNEG
33 RPOS
34 ICT
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.0
TYPE
O
O
O
O
I
DESCRIPTION
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT73LC00A is operating in
the HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT73LC00A is configured to operate in the HOST Mode, then this pin
functions as the LCV output pin by default. However, by using the on-chip Com-
mand Registers, this pin can be configured to function as the second Receive
Clock signal output pin RCLK2.
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73LC00A outputs data via the RPOS and RNEG out-
put pins on the rising edge of this clock signal.
NOTE: If the XRT73LC00A is operating in the HOST Mode and this pin is config-
ured to function as the additional Receive Clock signal output pin, then the
XRT73LC00A can be configured to update the data on the RPOS and RNEG
output pins on the falling edge of this clock signal.
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73LC00A outputs data via the RPOS and RNEG out-
put pins on the rising edge of this clock signal.
NOTE: If the XRT73LC00A is operating in the HOST Mode, the device can be
configured to update the data on the RPOS and RNEG output pins on the falling
edge of this clock signal.
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT73LC00A has received a Nega-
tive Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTES:
1. If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
2. This output pin is inactive if the XRT73LC00A has been configured to
operate in the Single-Rail Mode.
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT73LC00A has received a Posi-
tive Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
In-Circuit Test Input:
Setting this input pin “Low” causes all digital and analog outputs to go into a
high-impedance state in order to permit in-circuit testing. Set this pin “High” for
normal operation.
NOTE: This pin is internally pulled “High”.
8
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