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PDF XRT73L04B Data sheet ( Hoja de datos )

Número de pieza XRT73L04B
Descripción 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Fabricantes Exar Corporation 
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XRT73L04B
OCTOBER 2003
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
GENERAL DESCRIPTION
The XRT73L04B, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit is a low power CMOS version of the
XRT73L04A and consists of four independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04B can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04B performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L04A
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
Low Power CMOS design
5V tolerant I/O
-40°C to +85°C Operating Temperature Range
Available in a Thermally Enhanced 144 pin LQFP
package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
FIGURE 1. XRT73L04B BLOCK DIAGRAM
E3_(n) STS-1/DS3_(n)
Host/(HW) RLOL_(n) EXClk_(n) RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
AGC/
Equalizer
Slicer
Clock
Recovery
Invert
REQEN_(n)
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
Peak
Detector
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
HDB3/
B3ZS
Decoder
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
MTIP_(n)
MRing_(n)
DMO_(n)
Device
Monitor
Tx
Control
Channel 0
Channel 1
Channel 2
Channel 3
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT73L04B pdf
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
1.0 SELECTING THE DATA RATE ............................................................................................................... 25
1.1 CONFIGURING CHANNEL(N) ............................................................................................................ 25
Table 2:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ............................... 26
Table 3:Selecting the Data Rate for Channel(n) via the E3_(n) and STS-1/DS3_(n) input pins (Hardware Mode)
27
COMMAND REGISTER, CR4-(N) ........................................................................................................... 27
Table 4:Selecting the Data Rate for Channel(n) via the STS-1/DS3_(n) and the E3_(n) bit-fields within the Ap-
propriate Command Register (HOST Mode) ..................................................................................... 27
2.0 THE TRANSMIT SECTION ...................................................................................................................... 28
2.1 THE TRANSMIT LOGIC BLOCK ......................................................................................................... 28
Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 28
Figure 14. The typical interface for the Transmission of Data in a Dual-Rail Format from the Transmitting Ter-
minal Equipment to the Transmit Section of a channel .................................................................... 28
Figure 15.The XRT73L04B Samples the data on the TPData and TNData input pins ................................... 28
Accepting Single-Rail Data from the Terminal Equipment ................................................................ 29
COMMAND REGISTER CR3-(N) ............................................................................................................ 29
Figure 16.The Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is Accepting Sin-
gle-Rail Data from the Terminal Equipment ..................................................................................... 29
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................. 29
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................... 29
B3ZS Encoding .................................................................................................................................. 29
Figure 17.An Example of B3ZS Encoding ...................................................................................................... 30
HDB3 Encoding ................................................................................................................................. 30
Figure 18.An Example of HDB3 Encoding ..................................................................................................... 30
Disabling the HDB3/B3ZS Encoder ................................................................................................... 30
COMMAND REGISTER CR3-(N) ............................................................................................................ 31
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY .................................................................................... 31
Figure 19.The Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications .................... 31
Figure 20.The Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ... 32
Enabling the Transmit Line Build-Out Circuit ..................................................................................... 32
COMMAND REGISTER, CR1-(N) ........................................................................................................... 32
Disabling the Transmit Line Build-Out Circuit .................................................................................... 32
COMMAND REGISTER, CR1-(N) ........................................................................................................... 33
Design Guideline for Setting the Transmit Line Build-Out Circuit ...................................................... 33
The Transmit Line Build-Out Circuit and E3 Applications .................................................................. 33
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L04B TO THE LINE ...................................... 33
Figure 21.Recommended Schematic for Interfacing the Transmit Section of the XRT73L04B to the Line .... 33
TRANSFORMER RECOMMENDATIONS .................................................................................................... 34
3.0 THE RECEIVE SECTION ......................................................................................................................... 35
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L04B TO THE LINE ........................................ 35
Figure 22.Recommended Schematic for Interfacing the Receive Section of the XRT73L04B to the Line (Trans-
former-Coupling) .............................................................................................................................. 35
3.2 THE RECEIVE EQUALIZER BLOCK ................................................................................................... 36
Figure 23.The Typical Application for the System Installer ............................................................................ 36
Guidelines for Setting the Receive Equalizer ................................................................................... 36
II

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XRT73L04B arduino
RECEIVE INTERFACE
PIN #
NAME
80 RTIP_0
88 RTIP_1
101 RTIP_2
93 RTIP_3
82 REQEN_0
90 REQEN_1
99 REQEN_2
91 REQEN_3
110 RxClkINV
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
TYPE
I
I
I
DESCRIPTION
Receive TIP Input - Channel (n):
This input pin along with RRing_(n) is used to receive the bipolar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.
Receive Equalization Enable Input - Channel (n):
Setting this input pin "High" enables the Internal Receive Equalizer
within Channel (n). Setting this pin "Low" disables the Internal Receive
Equalizer. The guidelines for enabling and disabling the Receive Equal-
izer are described in Section 3.2.
NOTE: This pin is ignored and should be tied to GND if the XRT73L04B
is going to be operating in the HOST Mode, (internally pulled-down).
Invert RxClk_(n) Output - Select:
The function of this pin depends upon the mode of operation.
Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Chan-
nels to invert their RxClk_(n) clock output signals.
Setting this pin "Low" configures Channel(n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
Setting this input pin "High" configures Channel (n) to output the recov-
ered data via the RPOS_(n) and RNEG_(n) output pins on the falling
edge of RxClk_(n).
NOTE: This pin is internally pulled “High”.
CLOCK INTERFACE
PIN #
NAME
66 EXClk_0
57 EXClk_1
115 EXClk_2
123 EXClk_3
TYPE
I
DESCRIPTION
External Reference Clock Input - Channel (n):
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz
clock signal for DS3 applications or a 51.84 MHz clock signal for SONET
STS-1 applications.
The Channel (n) Clock Recovery PLL uses this signal as a Reference
Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The
Clock recovery PLL also generates the exact clock for the LIU.
It is permissible to use the same clock that drives the TxClk_(n) input
pin.
It is permissible to operate the four Channels at different data rates.
7

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