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PDF XRT73L03B Data sheet ( Hoja de datos )

Número de pieza XRT73L03B
Descripción 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Fabricantes Exar Corporation 
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XRT73L03B
OCTOBER 2003
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
GENERAL DESCRIPTION
The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line In-
terface Unit is a low power CMOS version of the
XRT73L03A and consists of three independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L03B can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L03B performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L03A
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
Low power CMOS design
5V tolerant I/O
-40°C to +85°C Operating Temperature Range
Available in a 120 pin LQFP package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
FIGURE 1. XRT73L03B BLOCK DIAGRAM
E3_(n)
STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
REQEN_(n)
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
TTIP_(n)
TRing_(n)
MTIP_(n)
MRing_(n)
DMO_(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
Device
Monitor
Pulse
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Channel 2 - (n) = 2
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT73L03B pdf
XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
3.4 THE HDB3/B3ZS DECODER ............................................................................................................................. 38
3.4.1 B3ZS Decoding (DS3/STS-1 Applications) .......................................................................................... 38
3.4.2 HDB3 Decoding (E3 Applications) ....................................................................................................... 38
3.4.3 Configuring the HDB3/B3ZS Decoder ................................................................................................. 39
COMMAND REGISTER CR2-(N) ...................................................................................................... 39
3.5 LOS DECLARATION/CLEARANCE ....................................................................................................................... 39
3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications ............................................................... 40
3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications .......................................... 41
COMMAND REGISTER CR0-(N) ...................................................................................................... 42
COMMAND REGISTER CR2-(N) ...................................................................................................... 42
COMMAND REGISTER CR0-(N) ...................................................................................................... 42
COMMAND REGISTER CR2-(N) ...................................................................................................... 42
3.5.3 Muting the Recovered Data while the LOS is being Declared ............................................................. 42
COMMAND REGISTER CR3-(N) ...................................................................................................... 43
3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .............. 43
3.6.1 Routing Dual-Rail Format Data to the Receiving Terminal Equipment ................................................ 43
COMMAND REGISTER CR3-(N) ...................................................................................................... 45
3.6.2 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment .............. 45
COMMAND REGISTER CR3-(N) ...................................................................................................... 45
3.7 SHUTTING OFF THE RECEIVE SECTION ............................................................................................................. 46
COMMAND REGISTER CR3-(N) ...................................................................................................... 46
4.0 Diagnostic Features of the XRT73L03B ......................................................................................... 47
4.1 THE ANALOG LOCAL LOOP-BACK MODE ............................................................................................................ 47
4.2 THE DIGITAL LOCAL LOOP-BACK MODE. ........................................................................................................... 48
COMMAND REGISTER CR4-(N) ...................................................................................................... 48
COMMAND REGISTER CR4-(N) ...................................................................................................... 48
4.3 THE REMOTE LOOP-BACK MODE ...................................................................................................................... 49
COMMAND REGISTER CR4-(n) ...................................................................................................... 49
4.4 TXOFF FEATURES ........................................................................................................................................... 50
COMMAND REGISTER CR1-(N) ...................................................................................................... 50
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ....................................................................................................... 50
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE .................................................................................................... 51
5.0 The Microprocessor Serial Interface .............................................................................................. 51
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................................... 51
COMMAND REGISTER CR1-(N) ...................................................................................................... 51
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ........................................................................... 53
5.2.1 Command Register - CR0-(n) .............................................................................................................. 53
COMMAND REGISTER CR0-(N) ....................................................................................................... 53
COMMAND REGISTER CR1-(N) ...................................................................................................... 53
5.2.3 Command Register CR2-(n) ................................................................................................................ 54
COMMAND REGISTER CR2-(N) ...................................................................................................... 54
COMMAND REGISTER CR3-(N) ...................................................................................................... 54
COMMAND REGISTER CR4-(N) ...................................................................................................... 55
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................................... 56
ORDERING INFORMATION ............................................................................................. 58
PACKAGE DIMENSIONS ................................................................................................. 58
REVISION HISTORY ..................................................................................................................................... 59
II

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XRT73L03B arduino
XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
CONTROL AND ALARM INTERFACE
PIN #
NAME
TYPE
31 MRing_0
4 MRing_1
15 MRing_2
I
30 MTIP_0
5 MTIP_1
16 MTIP_2
I
38 DMO_0
120 DMO_1
21 DMO_2
O
36 TAOS_0
6 TAOS_1
7 TAOS_2
I
55 RLOS_0
107 RLOS_1
58 RLOS_2
57 RLOL_0
105 RLOL_1
60 RLOL_2
56 LCV_0
106 LCV_1
59 LCV_2
66 ICT
O
O
O
I
67 LOSTHR_0
89 LOSTHR_1
75 LOSTHR_2
I
DESCRIPTION
Monitor Ring Input - Channel (n):
The bipolar line output signal from TRing_(n) can be connected to this
pin via a 270-ohm resistor in order to check for line driver failure. This
pin is internally pulled "High".
Monitor Tip Input - Channel (n):
The bipolar line output signal from TTIP_(n) can be connected to this pin
via a 270-ohm resistor in order to check for line driver failure. This pin is
internally pulled "High".
Drive Monitor Output - Channel (n):
If no transmitted AMI signal is present on MTIP_(n) and MRing_(n) input
pins for 128±32 TxClk periods, then DMO_(n) toggles and remains
"High" until the next AMI signal is detected.
Transmit All Ones Select - Channel (n):
A "High" on this pin causes the Transmit Section, within Channel (n), to
generate and transmit a continuous AMI all “1’s" pattern onto the line.
The frequency of this "1’s" pattern is determined by TxClk_(n).
This input pin is ignored if the XRT73L03B is operating in the HOST
Mode.
NOTE: This pin should be tied to GND if the XRT73L03B is going to be
operating in the HOST Mode, (internally pulled-down).
Receive Loss of Signal Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n) has detected a Loss of Sig-
nal Condition in the incoming line signal.
The criteria that the XRT73L03B uses to declare an LOS Condition
depends upon whether the device is operating in the E3 or STS-1/DS3
Mode.
Receive Loss of Lock Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n) has detected a Loss of Lock
Condition. Channel (n) declares an LOL (Loss of Lock) Condition if the
recovered clock frequency deviates from the Reference Clock frequency
(available at the EXClk(n) input pin) by more than 0.5%.
Line Code Violation Indicator - Channel 0:
Whenever the Receive Section of Channel (n) detects a Line Code Vio-
lation, it pulses this output pin "High". This output pin remains "Low" at
all other times.
NOTE: The XRT73L03B outputs an NRZ pulse via this output pin. It is
advisable to sample this output pin via the RxClk_(n) clock output signal.
In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a
high-impedance state to allow for in-circuit testing. This pin should be
set to "High" for normal operation.
This pin is internally pulled "High".
Loss of Signal Threshold Control - Channel (n):
Forcing the LOSTHR_(n) pin to GND or VDD provides two settings. This
pin must be set to a “High” or “Low” level upon power up and should not
be changed during operation.
This pin is only applicable during DS3 or STS-1 operations.
9

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