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PDF XRT73L03 Data sheet ( Hoja de datos )
| Número de pieza | XRT73L03 | |
| Descripción | 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT73L03
AUGUST 2000
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
GENERAL DESCRIPTION
The XRT73L03 is a 3-Channel, E3/DS3/STS-1 Line
Interface Unit designed for E3, DS3 or SONET STS-1
applications and consists of three independent line
transmitters and receivers integrated on a single chip.
Each channel of the XRT73L03 can be configured to
support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or
the SONET STS-1 (51.84 Mbps) rates. Each channel
can be configured to operate in a mode/data rate that
is independent of the other channels.
In the transmit direction, each channel in the
XRT73L03 encodes input data to either B3ZS or
HDB3 format and converts the data into the appropri-
ate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
In the receive direction, the XRT73L03 can perform
Equalization on incoming signals, perform Clock Re-
covery, decode data from either B3ZS or HDB3 for-
mat, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and de-
clare the occurrence of Line Code Violations.
APPLICATIONS
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
• Multiplexers
• ATM Switches
FEATURES
• Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Contains a 4-Wire Microprocessor Serial Interface
• Uses Minimum External components
• Single +3.3V Power Supply
• 5V tolerant I/O
• -40°C to +85°C Operating Temperature Range
• Available in a Thermally Enhanced 120 pin TQFP
package
FIGURE 1. XRT73L03 BLOCK DIAGRAM
E3_Ch(n) STS-1/DS3_Ch(n) Host/(HW) RLOL(n) EXClk(n)
RxOFF
RxClkINV
RTIP(n)
RRing(n)
REQEN(n)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
TTIP(n)
TRing(n)
MTIP(n)
MRing(n)
DMO(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
Device
Monitor
Pulse
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Channel 3 - (n) = 3
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
TxOFF(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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PRELIMINARY
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L03
REV. P1.0.13
COMMAND REGISTER CR1-(N) ...................................................................................................... 32
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit ................................................ 32
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications ............................................................. 32
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L03 TO THE LINE .......................................................... 32
Figure 16. Recommended Schematic for Interfacing the Transmit Section of the XRT73L03 to the Line ..... 32
TRANSFORMER VENDOR INFORMATION ........................................................................................... 33
3.0 The Receive Section ........................................................................................................................ 33
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L03 TO THE LINE ............................................................ 33
Figure 17. Recommended Schematic for Transformer-Coupling the Receive Section of the XRT73L03 to the
Line ............................................................................................................................................... 34
Figure 18. Recommended Schematic for Capacitive-Coupling the Receive Section of the XRT73L03 to the Line
....................................................................................................................................................... 34
3.2 THE RECEIVE EQUALIZER BLOCK ..................................................................................................................... 35
Figure 19. The Typical Application for the System Installer ........................................................................... 35
COMMAND REGISTER CR2_(N) ...................................................................................................... 36
3.3 CLOCK RECOVERY PLL ................................................................................................................................... 36
3.3.1 The Training Mode ............................................................................................................................. 36
3.3.2 The Data/Clock Recovery Mode ....................................................................................................... 36
3.4 THE HDB3/B3ZS DECODER ............................................................................................................................ 36
3.4.1 B3ZS Decoding DS3/STS-1 Applications ......................................................................................... 36
Figure 20. An Example of B3ZS Decoding ..................................................................................................... 37
3.4.2 HDB3 Decoding E3 Applications ...................................................................................................... 37
Figure 21. An Example of HDB3 Decoding .................................................................................................... 37
3.4.3 Configuring the HDB3/B3ZS Decoder .............................................................................................. 37
COMMAND REGISTER CR2-(N) ...................................................................................................... 38
3.5 LOS DECLARATION/CLEARANCE ...................................................................................................................... 38
3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications ........................................................ 38
Figure 22. The Signal Levels at which the XRT73L03 declares and clears LOS ........................................... 39
Figure 23. The Behavior the LOS Output Indicator in response to the Loss of Signal and the Restoration of Sig-
nal ................................................................................................................................................. 39
3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications ................................... 40
TABLE 5: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN FOR DS3 AND STS-1 APPLICATIONS .............................................................. 40
COMMAND REGISTER CR0-(N) ...................................................................................................... 40
COMMAND REGISTER CR2-(N) ...................................................................................................... 41
COMMAND REGISTER CR0-(N) ...................................................................................................... 41
COMMAND REGISTER CR2-(N) ...................................................................................................... 41
3.5.3 Muting the Recovered Data while the LOS is being Declared ....................................................... 41
COMMAND REGISTER CR3-(N) ...................................................................................................... 42
3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT ............. 42
3.6.1 Routing Dual-Rail Format Data to the Receiving Terminal Equipment ......................................... 42
Figure 24. The typical interface for the Transmission of Data in a Dual-Rail Format from the Receive Section of
the XRT73L03 to the Receiving Terminal Equipment .................................................................. 42
Figure 25. How the XRT73L03 outputs data on the RPOS and RNEG output pins ....................................... 43
Figure 26. The Behavior of the RPOS, RNEG and RxClk signals when RxClk is inverted ............................ 43
COMMAND REGISTER CR3-(N) ...................................................................................................... 44
3.6.2 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment ..... 44
COMMAND REGISTER CR3-(N) ...................................................................................................... 44
Figure 27. The typical interface for Data Transmission in a Single-Rail Format from the Receive Section of the
XRT73L03 to the Receiving Terminal Equipment ........................................................................ 44
Figure 28. The behavior of the RPOS and RxClk output signals while the XRT73L03 is transmitting Single-Rail
data to the Receiving Terminal Equipment .................................................................................. 45
3.7 SHUTTING OFF THE RECEIVE SECTION ............................................................................................................. 45
COMMAND REGISTER CR3-(N) ...................................................................................................... 45
4.0 Diagnostic Features of the XRT73L03 ............................................................................................ 46
4.1 THE ANALOG LOCAL LOOP-BACK MODE .......................................................................................................... 46
II
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PRELIMINARY
PIN DESCRIPTION
PIN #
47
SIGNAL NAME
EXClk1
48 RxDVDD1
49 RxClk1
50 RNEG1
51 RPOS1
52 NC
53 NC
54 RxDGND1
55 RLOS1
56 LCV1
57 RLOL1
58 RLOS3
59 LCV3
60 RLOL3
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L03
REV. P1.0.13
TYPE
I
****
O
O
O
****
O
O
O
O
O
O
DESCRIPTION
External Reference Clock Input - Channel 1:
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock sig-
nal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 appli-
cations.
The Clock Recovery PLL in Channel 1 uses this signal as a Reference Signal
for Declaring and Clearing the Receive Loss of Lock Alarm.
NOTES:
1. It is permissible to use the same clock which is also driving the TxClk
input pin.
2. It is permissible to operate the three Channels at different data rates.
Receive Digital 3.3V+ 5% VDD (for Receiver 1):
Receive Clock Output - Channel 1:
Refer to the description of pin 43, RxClk3
Receive Negative Data Output - Channel 1:
Refer to the description of pin 44, RNEG3
Receive Positive Data Output - Channel 1:
Refer to the description of pin 45, RPOS3
No Connection
No Connection
Receive Digital GND - Channel 1:
Receive Loss of Signal Output Indicator - Channel 1:
This output pin toggles "High" if Channel 1 in the XRT73L03 has detected a
Loss of Signal Condition in the incoming line signal.
The criteria the XRT73L03 uses to declare an LOS Condition depends upon
whether it is operating in the E3 or STS-1/DS3 Mode.
Line Code Violation Indicator - Channel 1:
Whenever the Receive Section of Channel 1 detects a Line Code Violation, it
pulses this output pin "High". This output pin remains "Low" at all other times.
NOTE: The XRT73L03 outputs an NRZ pulse via this output pin. It is advisable
to sample this output pin via the RxClk1 clock output signal.
Receive Loss of Lock Output Indicator - Channel 1:
This output pin toggles "High" if Channel 1 of the XRT73L03 has detected a
Loss of Lock Condition. Channel 1 declares an LOL (Loss of Lock) Condition if
the recovered clock frequency deviates from the Reference Clock frequency
(available at the EXClk(n) input pin) by more than 0.5%.
Receive Loss of Signal Output Indicator - Channel 3:
Refer to the description of pin 55, RLOS1
Line Code Violation Indicator - Channel 3:
Refer to the description of pin 56, LCV1
Receive Loss of Lock Output Indicator - Channel 3:
Refer to the description of pin 57, RLOL1
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| PDF Descargar | [ Datasheet XRT73L03.PDF ] | |
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