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PDF XRT7300 Data sheet ( Hoja de datos )
| Número de pieza | XRT7300 | |
| Descripción | E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT7300
FEBRUARY 2002
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
GENERAL DESCRIPTION
The XRT7300 DS3/E3/STS-1 Line Interface Unit is
designed to be used in DS3, E3 or SONET STS-1 ap-
plications and consists of a line transmitter and re-
ceiver integrated on a single chip.
XRT7300 can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT7300 encodes input
data to either B3ZS (for DS3/STS-1 applications) or
HDB3 (for E3 applications) format and converts the
data into the appropriate pulse shapes for transmis-
sion over coaxial cable via a 1:1 transformer.
In the receive direction the XRT7300 performs equal-
ization on incoming signals, performs Clock Recov-
ery, decodes data from either B3ZS or HDB3 format,
converts the receive data into TTL/CMOS format,
checks for LOS or LOL conditions and detects and
declares the occurrence of line code violations.
The XRT7300 also contains a 4-Wire Microprocessor
Serial Interface for accessing the on-chip Command
registers.
FEATURES
• Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Contains a 4-Wire Microprocessor Serial Interface
• Uses Minimum External components
• Requires Single +5V Power Supply
• -40°C to +85°C Operating Temperature Range
• Available in a 44 pin TQFP package
APPLICATIONS
• Interfaces to E3, DS3 or SONET STS-1 Networks
• CSU/DSU Equipment
• PCM Test Equipment
• Fiber Optic Terminals
• Multiplexers
NOTE: This Device is Protected by US Patent # 6,157,270
FIGURE 1. BLOCK DIAGRAM OF THE XRT7300
E3
STS-1/DS3
Host/(HW)
RLOL EXCLK
ICT RCLK2INV
RTIP
RRING
REQDIS
LOSTHR
SDI
SDO/(LCV)
SClk
CS
REGRESET
TTIP
TRING
MTIP
MRING
DMO
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
Device
Monitor
Pulse
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
RCLK1
LCV/(RCLK2)
RPOS
RNEG
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TClk
TXLEV
TXOFF
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7300
REV. 1.1.1
COMMAND REGISTER CR2 (ADDRESS = 0X02) .................................................................................. 33
Muting the Recovered Data while the LOS is being Declared............................................................. 33
3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .... 33
COMMAND REGISTER CR3 (ADDRESS = 0X03) .................................................................................. 33
Figure 23. The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Receive Section
of the XRT7300 to the Receiving Terminal Equipment ...................................................................... 34
Figure 24. How the XRT7300 Outputs Data on the RPOS and RNEG Output Pins ........................................ 34
Figure 25.The Behavior of the RPOS, RNEG and RCLK1 Signals When RCLK1 is Inverted ......................... 35
Routing Single-Rail Format data (Binary Data Stream) to the Receive Terminal Equipment ............. 35
COMMAND REGISTER CR3 (ADDRESS = 0X03) .................................................................................. 35
COMMAND REGISTER CR3 (ADDRESS = 0X03) .................................................................................. 35
Figure 26.The Typical Interface for the Transmission of Data in a Single-Rail Format From the Receive Section
of the XRT7300 to the Receiving Terminal Equipment ...................................................................... 36
Figure 27.The Behavior of the RPOS and RCLK1 Output Signals While the XRT7300 is Transmitting Single-Rail
Data to the Receiving Terminal Equipment........................................................................................ 36
4.0 DIAGNOSTIC FEATURES OF THE XRT7300 ........................................................................................ 36
4.1 THE ANALOG LOCAL LOOP-BACK MODE ................................................................................................. 36
Figure 28.The Analog Local Loop-Back in the XRT7300 ................................................................................. 37
COMMAND REGISTER CR4 (ADDRESS = 0X04) .................................................................................. 37
4.2 THE DIGITAL LOCAL LOOP-BACK MODE .................................................................................................. 37
Figure 29.The Digital Local Loop-Back path in the XRT7300 .......................................................................... 38
COMMAND REGISTER CR4 (ADDRESS = 0X04) .................................................................................. 38
4.3 THE REMOTE LOOP-BACK MODE ............................................................................................................ 38
Figure 30.The Remote Loop-Back Path in the XRT7300 ................................................................................. 39
COMMAND REGISTER CR4 (ADDRESS = 0X04) .................................................................................. 39
4.4 TXOFF FEATURES................................................................................................................................. 40
COMMAND REGISTER CR1 (ADDRESS = 0X01) .................................................................................. 40
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ............................................................................................ 40
Figure 31.The XRT7300 Employing the Transmit Drive Monitor Features....................................................... 40
Figure 32. Two LIU’s, Each Monitoring the Transmit Output Signal of the Other LIU IC ................................. 41
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE .......................................................................................... 41
COMMAND REGISTER CR1 (ADDRESS = 0X01) .................................................................................. 41
5.0 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 42
5.1 DESCRIPTION OF THE COMMAND REGISTERS .......................................................................................... 42
Table 5:Addresses and Bit Formats of XRT7300 Command Registers ........................................................... 42
DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER .................................................... 42
Command Register - CR0 ................................................................................................................... 42
Command Register - CR1 ................................................................................................................... 43
Command Register - CR2 ................................................................................................................... 44
Command Register - CR3 ................................................................................................................... 44
Command Register - CR4 ................................................................................................................... 45
5.2 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ......................................................................... 45
Table 6:Loop-Back Modes................................................................................................................................ 45
Figure 33.Microprocessor Serial Interface Data Structure ............................................................................... 46
Figure 34. How to Interface the XRT7300 IC to the XRT7234/45 E3/DS3 ATM UNI IC .................................. 47
Figure 35.How to Interface the XRT7300 IC to the XRT7250 DS3/E3 Framer IC............................................ 48
ORDERING INFORMATION ..................................................................................................................... 49
Package Dimensions ....................................................................................................... 49
III
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PIN DESCRIPTION
PIN #
SYMBOL
27 EXCLK
28 GND
29 VDD
30 LCV/(RCLK2)
31 RCLK1
32 RNEG
33 RPOS
34 ICT
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
TYPE
I
****
****
O
O
O
O
I
DESCRIPTION
External Reference Clock Input:
Apply a 34.368MHz clock signal for E3 applications, a 44.736 MHz clock signal
for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications.
Receiver Digital Ground
Receiver Digital VDD
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT7300 is operating in the
HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT7300 is configured to operate in the HOST Mode, then this pin func-
tions as the LCV output pin by default. However, by using the on-chip Command
Registers, this pin can be configured to function as the second Receive Clock
signal output pin (RCLK2).
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT7300 is operating in the HOST Mode and this pin is configured
to function as the additional Receive Clock signal output pin, then the XRT7300
can be configured to update the data on the RPOS and RNEG output pins on the
falling edge of this clock signal.
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT7300 device is operating in the “Host” Mode, then the user can
configure the device to update the data on the RPOS and RNEG output pins on
the falling edge of this clock signal.
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Negative
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Positive
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
In-Circuit Test Input:
Setting this pin “Low” causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. This pin is internally pulled “High”.
7
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| PDF Descargar | [ Datasheet XRT7300.PDF ] | |
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