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PDF XR19L200 Data sheet ( Hoja de datos )
| Número de pieza | XR19L200 | |
| Descripción | SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
APRIL 2006
REV. P1.0.2
GENERAL DESCRIPTION
The XR19L200 (L200) is a highly integrated device that
combines a single channel Universal Asynchronous
Receiver and Transmitter (UART) and an RS-232
transceiver. The L200 is designed to operate with a single
3.3V or 5V power supply. The L200 is fully compliant with
EIA/TIA-232-F Standards from a +3.0V to +5.5V power
supply. The device operates at 250 Kbps data rate with
worst case 3K ohms load. Both RS-232 driver outputs and
receiver inputs can operate in harsh electrical environments
of +/-15V without damage and can survive multiple +/-15kV
ESD on the RS-232 lines, while maintaining RS-232 output
levels.
The L200 operates in three different modes: Awake, Partial
Sleep, and Full Sleep. Each mode can be invoked via
hardware or software. In the Awake mode, all functions are
active. In the Partial Sleep mode, the internal crystal
oscillator or charge pump is turned off. In Full Sleep mode,
the internal crystal oscillator and the charge pump is shut
down. All the RS-232 receivers remain active in any of
these four modes.
APPLICATIONS
• Battery-Powered Equipment
• Handheld and Mobile Devices
• Handheld Terminals
• Industrial Peripheral Interfaces
• Point-of-Sale (POS) Systems
FEATURES
• Meets true EIA/TIA-232-F Standards from a 3.0 V to 5.5V
operation
• Up to 250 Kbps data transmission rate
• 45us sleep mode exit (charge pump to full power)
• ESD protection for RS-232 I/O pins at
■ +/-15kV - Human Body Model
■ +/-15kV - IEC 1000-4-2, Air-Gap Discharge
■ +/- 8kV - IEC 1000-4-2, Contact Discharge
• Software compatible with industry standard 16550 UART
• Intel/Motorola bus select
• Quarter-modem interface (TXD, RXD)
• Sleep modes to conserve battery power
• Wake-up interrupt upon exiting low power modes
FIGURE 1. BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CS#
INT (IRQ#)
RESET (RESET#)
I/M#
Crystal
Osc/Buffer
BRG
16 Byte
TX FIFO
16 Byte
RX FIFO
TX
RX
*5 V
Tolerant
Inputs
UART
Modem
I/Os
XR19L200
Charge Pump
5K
VREF+
VREF-
TXD
RXD
RS-232 Transceiver
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
PRELIMINARY
XR19L200
REV. P1.0.2
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
1.0 PRODUCT DESCRIPTION
The XR19L200 interface converter consists of a full-functional UART with 16 bytes of transmit and receive
FIFO, a charge pump, two RS-232 drivers, two RS-232 receivers, and a sleep mode circuitry. It operates from
a single +3V to 5.5V supply at 250Kbps data rate, while meeting all EIA RS-232F specifications. Its feature set
is fully compatible to the XR16L580 device. Unlike the XR16L580, the modem signals are not CMOS/TTL
level, but conform to EIA/TIA 232 or RS-232 voltage levels. The configuration registers set is 16550 UART
compatible for control, status and data transfer. Also, the L200 has 16-bytes of transmit and receive FIFOs,
automatic Xon/Xoff and special character software flow control, transmit and receive FIFO trigger levels, and a
programmable baud rate generator with a prescaler of divide by 1 or 4. Additionally, the L200 includes the ACP
pin which the user can shut down the charge pump for the RS-232 drivers when the L200 is already in sleep
mode. The L200 is fabricated using an advanced CMOS process.
Enhanced Features
The L200 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L200 is
designed to work with low supply voltage and high performance data communication systems that require fast
data processing time. Increased performance is realized in the L200 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time.
Intel or Motorola Data Bus Interface
The L200 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface.
The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#,
IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#
and CS# signals for data bus transactions. See pin description section for details on all the control signals. The
Intel and Motorola bus interface selection is made through the pin, I/M#.
Data Rate
The L200 is capable of operation up to 250Kbps data rate using the 16X internal sampling clock rate. The
UART section can operate at much higher speeds, but the speed of the RS-232 transceiver is limited to
250Kbps beyond which the L200 cannot comply with the EIA/TIA-232 electrical characteristics. The device can
operate either with a crystal on pins XTAL1 and XTAL2, or external clock source on XTAL1 pin.
Internal Enhanced Register Sets
The L200 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, modem interface controls and status, and
sleep mode are all standard features. Following a power on reset or an external reset (and operating in 16 or
Intel Mode), the registers defaults to the reset condition and is compatible with the XR16L580.
RS-232 Interface
The L200 includes RS-232 drivers/receivers for the TXD and RXD signals (If more modem input and output
signals are needed, see the XR19L220 and XR19L210). This feature eliminates the need for an external RS-
232 transceiver. The charge pump provides output voltages of +5V and -5V for its drivers over the 3.0V to 5.5V
VCC supply voltage. The serial output TX swings between -5V (inactive) and 5V (active) RS-232 voltage
levels. The serial input RX is an RS-232 receiver and can take any voltage swing from -15V to +15V. The
receiver is always active, even in Partial or Full Sleep modes. The RS-232 drivers guarantee a data rate of
250Kbps even when fully loaded with 3Kohm in parallel with 1000pF load. Also, the slew rate of the driver
output is internally limited to a maximum of 30V/us in order to meet the EIA-232F standard.
5
5 Page 
PRELIMINARY
XR19L200
REV. P1.0.2
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the
host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as
defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is
enabled by IER bit-0.
2.11.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
2.12 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 10), the L200 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the L200 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the L200 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the L200 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 10) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the L200 compares two consecutive receive characters with two software flow control 8-bit
values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow
control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or
FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L200 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L200 sends the
Xoff character(s) two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level. To clear this condition, the L200 will transmit the
programmed Xon character(s) as soon as receive FIFO is less than one trigger level below the programmed
trigger level (see Table 8). The table below describes this.
11
11 Page | ||
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| PDF Descargar | [ Datasheet XR19L200.PDF ] | |
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