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PDF XR17V254 Data sheet ( Hoja de datos )

Número de pieza XR17V254
Descripción 66MHZ PCI BUS QUAD UART
Fabricantes Exar Corporation 
Logotipo Exar Corporation Logotipo



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XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
FEBRUARY 2007
REV. 1.0.0
GENERAL DESCRIPTION
The XR17V2541 (V254) is a single chip 4-channel
66MHz PCI (Peripheral Component Interconnect)
UART (Universal Asynchronous Receiver and
Transmitter) solution, optimized for higher
performance and lower power. The V254 device with
its fifth generation register set is designed to meet the
high bandwidth and power management
requirements for multi-serial communication ports for
system administration and management. The 32-bit
66MHz PCI interface is compliant with PCI 3.0 and
PCI power management revision 1.1 specifications.
The device provides an upgrade path for Exar’s
33MHz 5V and Universal PCI UART family of
products in a 144-pin LQFP package.
The V254 consists of four independent UART
channels, each with set of configuration and
enhanced registers, 64 bytes of Transmit (TX) and
Receive (RX) FIFOs, and a fractional Baud Rate
Generator (BRG). A global interrupt source register
provides a complete interrupt status indication for all
4 channels to speed up interrupt parsing. The V254
device operates at 33/66MHz and features fully
programmable TX and RX FIFO level triggers,
automatic hardware and software flow control, and
automatic RS-485 half duplex direction control output
for software and hardware design simplification.
NOTE 1: Covered by U.S. Patents #5,649,122 and #5,949,787
APPLICATIONS
Remote Access Servers
Storage Network Management
Factory Automation and Process Control
Instrumentation
Multi-port RS-232/RS-422/RS-485 Cards
Point-Of-Sales
FEATURES
High performance 32-bit 66MHz PCI UART
PCI 3.0 compliance
PCI power management rev. 1.1 compliance
EEPROM interface for PCI configuration
3.3V supply with 5V tolerant non-PCI (serial) inputs
Data read/write burst operation
Global interrupt register for all four UART channels
Up to 8 Mbps serial data rate
Eight multi-purpose inputs/outputs
A 16-bit general purpose timer/counter
Sleep mode with wake-up Indicator
Four independent UART channels controlled with
16C550 compatible register Set
64-byte TX and RX FIFOs with level counters
and programmable trigger levels
Fractional baud rate generator
Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
Automatic Xon/Xoff software flow control
RS-485 half duplex direction control output
with selectable turn-around delay
Infrared (IrDA 1.0) data encoder/decoder
FIGURE 1. BLOCK DIAGRAM OF THE XR17V254
3.3V VCC
CLK (upto
66MHz)
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
IDSEL
PERR#
SERR#
PAR
INTA#
PME#
EECK
EEDI
EEDO
EECS
GND
PCI Local
Bus
Interface
Device
Configuration
Registers
Configuration
Space
Registers
EEPROM
Interface
16-bit
Timer/Counter
UART Channel 0
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel 1
(5V Tolerant
Serial Inputs)
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
UART Channel 2
UART Channel 3
Multi-pu.rpose
Inputs/Outputs
Crystal Osc/Buffer
TX3, RX3, DTR3#,
DSR3#, RTS3#,
CTS3#, CD3#, RI3#
MPIO0- MPIO7
XTAL1
XTAL2
TMRCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XR17V254 pdf
REV. 1.0.0
PIN DESCRIPTIONS
XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
NAME
RI3#
PIN #
59
TYPE
DESCRIPTION
I UART channel 3 Ring Indicator or general purpose input (active LOW).
ANCILLARY SIGNALS
MPIO0
108 I/O Multi-purpose input/output 0. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
MPIO1
107 I/O Multi-purpose input/output 1. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO2
74 I/O Multi-purpose input/output 2. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO3
73 I/O Multi-purpose input/output 3. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO4
68 I/O Multi-purpose input/output 4. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO5
67 I/O Multi-purpose input/output 5. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO6
66 I/O Multi-purpose input/output 6. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO7
65 I/O Multi-purpose input/output 7. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
EECK
116 O Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for
reading the vendor and sub-vendor ID during power up or reset. However, it
can be manually clocked thru the Configuration Register REGB.
EECS
115 O Chip select to a EEPROM device like 93C46. It is manually selectable thru
the Configuration Register REGB. Requires a pull-up 4.7K ohm resistor for
external sensing of EEPROM during power up. See DAN112 for further
details.
EEDI
114 O Write data to EEPROM device. It is manually accessible thru the Configura-
tion Register REGB.
EEDO
113 I Read data from EEPROM device. It is manually accessible thru the Configu-
ration Register REGB.
XTAL1
110 I Crystal or external clock input.
XTAL2
109 O Crystal or buffered clock output.
TMRCK
69 I 16-bit timer/counter external clock input.
ENIR
70 I Infrared mode enable (active high). This pin is sampled during power up, fol-
lowing a hardware reset (RST#) or soft-reset (register RESET). It can be
used to start up all 4 UARTs in the infrared mode. The sampled logic state is
transferred to MCR bit [6] in the UART.
VCC
64, 90,112, 4,
19, 34, 45, 137
Power supply for the UART core logic and PCI bus I/O - 3.3V only. The V254
is PCI 3.0 signalling compliant at 3.3V operation. The non-PCI inputs (except
XTAL1) are 5V tolerant. This includes all the serial (modem) inputs.
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XR17V254 arduino
REV. 1.0.0
ADDRESS
OFFSET
BITS
14:9
8
7:2
1:0
TYPE
RO
RWR
RO
RWR
XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
TABLE 2: POWER MANAGEMENT REGISTERS
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
Reserved
00000b
PME_Enable
0b
Reserved
000000b
PowerState
00b
NOTE: RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-Clear.
1.2.1 Power States and Power State Transitions of the V254
The XR17V254 supports D0, D3hot and D3cold power states and is capable of generating the PME# signal
from the D3hot state. The following paragraphs describe these power states and Figure 4 shows the power
state transitions of the V254.
D0 STATE
The XR17V254 must be placed in the D0 state before being used in a system. The D0 state represents two
states - D0 Uninitalized and D0 Active. Upon entering D0 from power up or transition from D3hot, the V254 will
be in the D0 Uninitialized state. Once initialized by the system software, the V254 will enter the D0 Active state.
In the D0 Active state, the V254 is fully functional and will respond to all PCI bus transactions as well as issue
interrupts (INTA#). The system software can program the V254 to enter the D3hot state from the D0 state.
D3HOT STATE
The V254 enters the D3hot state when the system software programs the V254 from D0 to D3hot. In this state,
the V254 will not be fully functional. The V254 will respond only to PCI configuration space accesses, if a PCI
clock is provided and will not respond to PCI memory accesses nor will it issue interrupts. However, the V254
will continue to receive data and the automatic software and hardware flow control, if enabled, will continue to
function normally. While in the D3hot state, the V254 asserts the PME# (Power Management Event) signal, if
enabled by setting PME_Enable bit, upon one of the following events:
RX pin of any of the channels goes LOW (START bit detected), or
Any of the delta bits of modem inputs (MSR register bits [3:0]) is set in any of the 4 channels (see
page 49)
The V254 also sets the PME_Status bit when such an event occurs, regardless of whether the PME_Enable bit
is set or not. The system software can reset the PME_Status bit by writing a ’1’ to it. When the system software
programs the V254 from D3hot to D0, typically in response to the PME# signal, the V254 enters the D0 Active
state and will retain all the values of its internal registers. The V254 will keep its PCI signal drivers disabled for
the duration of the D3hot to D0 Uninitialized state transition. The V254 saves the PME context (configuration
registers and functional state information) in the D3hot state.
Note: The V254 has a sleep mode which keeps the power consumption to a minimum (see Sleep Mode
description on page 22). This is independent of the power state the V254 is in. The user can optionally place
the V254 in sleep mode (via the software driver) in the Active D0 state anytime or specifically when the system
software commands the V254 to enter the D3hot state. The crystal oscillator shuts down when the conditions
given in Sleep Mode section on page 22 are satisfied, and re-starts when one of the events as described in the
same section occurs. Upon re-starting, the oscillator may take a long time to settle. This time may be more
than 20ms which is the maximum wait time guaranteed by the system software before resuming normal PCI
bus transactions in the Active D0 state. Therefore, there may be data errors if the V254 is commanded to
transmit data before the oscillator is ready. It is recommended not to use sleep mode while in the D3hot
state for this reason.
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