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PDF XR17V252 Data sheet ( Hoja de datos )
| Número de pieza | XR17V252 | |
| Descripción | 66MHZ PCI BUS DUAL UART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR17V252
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
MARCH 2006
REV. 1.0.1
GENERAL DESCRIPTION
The XR17V2521 (V252) is a single chip 2-channel
66MHz PCI UART (Universal Asynchronous Receiver
and Transmitter) solution, optimized for higher
performance and lower power. The V252 device with
its fifth generation register set is designed to meet the
high bandwidth and power management
requirements for multi-serial communication ports for
system administration and management. The 32-bit
66MHz PCI interface is compliant with PCI 3.0 and
PCI power management revision 1.1 specifications.
The device provides an upgrade path for Exar’s
33MHz 5V and Universal PCI UART family.
The V252 consists of two independent UART
channels, each with set of configuration and
enhanced registers, 64 bytes of Transmit (TX) and
Receive (RX) FIFOs, and a fractional Baud Rate
Generator (BRG). A global interrupt source register
provides a complete interrupt status indication for
both channels to speed up interrupt parsing. The
V252 device operates at 33/66MHz and features fully
programmable TX and RX FIFO level triggers,
automatic hardware and software flow control, and
automatic RS-485 half duplex direction control output
for software and hardware design simplification.
NOTE 1: Covered by U.S. Patents #5,649,122 and #5,949,787
APPLICATIONS
• Remote Access Servers
• Storage Network Management
• Factory Automation and Process Control
• Instrumentation
FIGURE 1. BLOCK DIAGRAM OF THE XR17V252
• Multi-port RS-232/RS-422/RS-485 Cards
• Point-of-Sale Systems
FEATURES
• High performance 32-bit 66MHz PCI UART
• PCI 3.0 compliant
• PCI power management rev. 1.1 compliant
• EEPROM interface for PCI configuration
• 3.3V supply with 5V tolerant non-PCI (serial) inputs
• Data read/write burst operation
• Global interrupt register for both UART channels
• Up to 8 Mbps serial data rate
• Eight multi-purpose inputs/outputs
• A 16-bit general purpose timer/counter
• Sleep mode with wake-up Indicator
• Two independent UART channels controlled with
■ 16C550 compatible register Set
■ 64-byte TX and RX FIFOs with level counters
and programmable trigger levels
■ Fractional baud rate generator
■ Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
■ Automatic Xon/Xoff software flow control
■ RS-485 half duplex direction control output
with selectable turn-around delay
• Infrared (IrDA 1.0) data encoder/decoder
3.3 V VCC
CLK( up to
66 MHz)
RST#
A D[ 31: 0]
C/ BE[ 3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
INTA#
IDSEL
PERR#
SERR#
PAR
PME#
EECK
EEDI
EEDO
EECS
ENIR
EN 4 8 5#
PCI Local
Bus
Interface
Device
Configuration
Registers
Configuration
Space
Registers
EEPROM
Interface
16- bit
Timer/Counter
UART Channel 0
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel 1
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
(5 V Tolerant
Serial Inputs)
TX0 , RX0 , DTR0#,
DSR0 #, RTS0#,
CTS0 #, CD0 #, RI0#
TX1 , RX1 , DTR1#,
DSR1 #, RTS1#,
CTS1 #, CD1 #, RI1#
Multi- pu. rpose
Inputs/ Outputs
Crystal Osc / Buffer
MPIO0 - MPIO7
XTAL1
XTAL2
TMRCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.1
PIN DESCRIPTIONS
XR17V252
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
NAME
ENIR
EN485#
PME#
PIN #
74
65
79
TYPE
I
I
OD
DESCRIPTION
Global Infrared mode enable (active high). This pin is sampled during power
up, following a hardware reset (RST#) or soft-reset (register RESET). It can
be used to start up both UARTs in the infrared mode. The sampled logic state
is transferred to MCR bit-6 in the UART. Software can override this pin there-
after and enable or disable it.
Global AutoRS485 half-duplex direction control enable (active low). During
power up or reset, this pin is sampled and if it is a logic high, both UARTs are
set for Auto RS485 Mode. Also, the Auto RS485 bit, FCTR[5], is set in both
channels. Software can override this pin thereafter and enable or disable it.
Power Management Event signal. While in D3hot state, if the PME_Enable bit
in the Power Management Control/Status Register is set, the V252 asserts
the PME# upon receiving a new character or upon change of state of modem
inputs on any channel.
VCC
54, 80, 10, 22, PWR Power supply for the UART core logic and PCI bus I/O - 3.3V only. The V252
32, 43, 89, 100
is PCI 3.0 signalling compliant at 3.3V operation. The non-PCI inputs (except
XTAL1) are 5V tolerant. This includes all the serial (modem) inputs.
GND
1, 11, 23, 33, PWR Power supply common, ground.
44, 53, 78, 88
NC 63, 64
No Connection.
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
XR17V252
REV. 1.0.1
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
D3COLD STATE
The V252 enters the state when power is removed from the device. All context is lost in this state and the V252
does not support PME# in this state. When power is restored, PCI RST# must be asserted and the V252 will
return to the D0 Uninitialized state with a full PCI 3.0 compliant power-on reset sequence. The V252 will set all
its registers and outputs to the power-on defaults just as at initial power up. The system software must then
fully initialize and re-configure the V252 to place it in the D0 Active state.
FIGURE 4. POWER STATE TRANSITIONS OF THE XR17V252
Power on +
PCI RST#
D0
Uninitialized
Power on +
PCI RST#
D0
Active
D3cold
D3hot
VCC Removed
1.3 Special Read/Write Register to store User Information
This 32-bit register can be used to store user information and is writable only via the EEPROM. This is
implemented at an offset of 0x48 in the PCI Configuration Space immediately following the Power
Management Registers. This register can be used to store application-specific information which may be used
by the device driver to initialize the device appropriately.
TABLE 3: SPECIAL READ/WRITE REGISTER
ADDRESS
OFFSET
0x48
BITS
31:0
TYPE
EWR
DESCRIPTION
User Information Writable only through EEPROM
RESET VALUE
(HEX)
0x00000000
NOTE: EWR=Read/Write from external EEPROM.
11
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