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PDF XR16V654 Data sheet ( Hoja de datos )

Número de pieza XR16V654
Descripción 2.25V TO 3.6V QUAD UART
Fabricantes Exar Corporation 
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XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
MAY 2007
REV. 1.0.1
GENERAL DESCRIPTION
The XR16V6541 (V654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, programmable transmit and receive FIFO
trigger levels, automatic hardware and software flow
control, and data rates of up to 16 Mbps at 4X
sampling rate. Each UART has a set of registers that
provide the user with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The V654 is available in a 48-
pin QFN, 64-pin LQFP, 68-pin PLCC, 80-pin LQFP
and 100-pin QFP packages. The 64-pin and 80-pin
packages only offer the 16 mode interface, but the
48, 68 and 100 pin packages offer an additional 68
mode interface which allows easy integration with
Motorola processors. The XR16V654IV (64-pin)
offers three state interrupt output while the
XR16V654DIV provides continuous interrupt output.
The 100 pin package provides additional FIFO status
outputs (TXRDY# and RXRDY# A-D), separate
infrared transmit data outputs (IRTX A-D) and
channel C external clock input (CHCCLK). The
XR16V654 is compatible with the industry standard
ST16C554 and ST16C654/654D.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C754B and Philip’s SC16C654B
Intel or Motorola Data Bus Interface select
Four independent UART channels
Register Set Compatible to 16C550
Data rates of up to 16 Mbps
64 Byte Transmit FIFO
64 Byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Progammable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
2.25V to 3.6V supply operation
Sleep Mode with automatic wake-up
Crystal oscillator or external clock input
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FIGURE 1. XR16V654 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
CLKSEL
Data Bus
Interface
* 5 Volt Tolerant Inputs
(Except XTAL1 input)
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc/Buffer
2.25V to 3.6V VCC
GND
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
654 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XR16V654 pdf
REV. 1.0.1
ORDERING INFORMATION
PART NUMBER
XR16V654IJ
XR16V654IV
XR16V654DIV
XR16V654IQ
XR16V654IL
XR16V654IV80
XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
PACKAGE
68-Lead PLCC
64-Lead LQFP
64-Lead LQFP
100-Lead QFP
48-pin QFN
80-Lead LQFP
OPERATING TEMPERATURE
RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
DEVICE STATUS
Active
Active
Active
Active
Active
Active
PIN DESCRIPTIONS
Pin Description
NAME
48-QFN
PIN #
64-LQFP 68-PLCC 80-LQFP 100-QFP
PIN #
PIN#
PIN #
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2 15 22 32 28 37 I Address data lines [2:0]. These 3 address
A1 16 23 33 29 38
A0 17 24 34 30 39
lines select one of the internal registers in
UART channel A-D during a data bus trans-
action.
D7 46 60 5 75 95 I/O Data bus lines [7:0] (bidirectional).
D6 45 59 4 74 94
D5 44 58 3 73 93
D4 43 57 2 72 92
D3 42 56 1 71 91
D2 41 55 68 70 90
D1 40 54 67 69 89
D0 39 53 66 68 88
IOR# 29 40 52 51 66 I When 16/68# pin is HIGH, the Intel bus
(VCC)
interface is selected and this input becomes
read strobe (active low). The falling edge
instigates an internal read cycle and
retrieves the data byte from an internal reg-
ister pointed by the address lines [A2:A0],
puts the data byte on the data bus to allow
the host processor to read it on the rising
edge.
When 16/68# pin is LOW, the Motorola bus
interface is selected and this input is not
used and should be connected to VCC.
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XR16V654 arduino
XR16V654/654D
REV. 1.0.1
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR16V654 (V654) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled and has its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 64 bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder
(IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and data rate
up to 16 Mbps. The XR16V654 can operate from 2.25 to 3.6 volts. The V654 is fabricated with an advanced
CMOS process.
Enhanced FIFO
The V654 QUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C554, or one byte in the ST16C454. The V654 is designed to work with high performance
data communication systems, that require fast data processing time. Increased performance is realized in the
V654 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control
mechanism. This allows the external processor to handle more networking tasks within a given time. For
example, the ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses
a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to
service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the V654, the data buffer will
not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the
programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Rate
The V654 is capable of operation up to 16 Mbps at 3.3V with 4Xinternal sampling clock rate. The device can
operate at 3.3V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock
source of 64 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user
can set the prescaler bit and sampling rate for data rates of up to 3.68 Mbps.
Enhanced Features
The rich feature set of the V654 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder
interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR
bit-3 can be configured to provide a software controlled or continuous interrupt capability. For backward
compatibility to the ST16C654, the 64-pin LQFP does not have the INTSEL pin. Instead, two different LQFP
packages are offered. The XR16V654DIV operates in the continuous interrupt enable mode by internally
bonding INTSEL to VCC. The XR16V654IV operates in conjunction with MCR bit-3 by internally bonding
INTSEL to GND.
The XR16V654 offers a clock prescaler select pin to allow system/board designers to preset the default baud
rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator.
It can then be overridden following initialization by MCR bit-7.
The 100 pin packages offer several other enhanced features. These features include a CHCCLK clock input,
FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal
operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate
register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for
each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels.
The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for
Infrared applications. These outputs are provided in addition to the standard asynchronous modem data
outputs.
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