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PDF XR16V2750 Data sheet ( Hoja de datos )
| Número de pieza | XR16V2750 | |
| Descripción | HIGH PERFORMANCE DUART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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PRELIMINARY
XR16V2750
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
JUNE 2006
REV. P1.0.0
GENERAL DESCRIPTION
The XR16V27501 (V2750) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 64 byte TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
ST16C2550 and XR16L2750. The V2750 register set
is identical to the XR16L2750 and is compatible to the
ST16C2550 and the XR16C2850 enhanced features.
It supports the Exar’s enhanced features of
programmable FIFO trigger level and FIFO level
counters, automatic hardware (RTS/CTS) and
software flow control, automatic RS-485 half duplex
direction control output and a complete modem
interface. Onboard registers provide the user with
operational status and data error flags. An internal
loopback capability allows system diagnostics.
Independent programmable baud rate generators are
provided in each channel to select data rates up to 8
Mbps at 3.3 Volt and 8X sampling clock. The V2750
is available in 48-pin TQFP and 32-pin QFN
packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 2.25 to 3.6 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s XR16L2750 and
TI’s TL16C752B in the 48-TQFP package
• Two independent UART channels
■ Register set compatible to XR16L2750
■ Data rate of up to 8 Mbps at at 3.3 V, and
6.25 Mbps at 2.5 V with 8X sampling rate
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 64 bytes
■ Programmable TX and RX FIFO Trigger Levels
■ Transmit and Receive FIFO Level Counters
■ Automatic Hardware (RTS/CTS) Flow Control
■ Selectable Auto RTS Flow Control Hysteresis
■ Automatic Software (Xon/Xoff) Flow Control
■ Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode
■ Full modem interface
• Device Identification and Revision
• Crystal oscillator (up to 32MHz) or external clock
(upto 64MHz) input
• 48-TQFP and 32-QFN packages
FIGURE 1. XR16V2750 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset
8-bit Data
Bus
Interface
* 5 Volt Tolerant Inputs
UART Channel A
UART 64 Byte TX FIFO
Regs
TX & RX
IR
ENDEC
BRG
64 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 3.6 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
2750BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. P1.0.0
Pin Description
PRELIMINARY
XR16V2750
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
NAME
RXB
32-QFN
PIN #
3
RTSB#
15
CTSB#
16
DTRB#
DSRB#
-
-
CDB#
-
RIB#
-
OP2B#
-
ANCILLARY SIGNALS
XTAL1
10
XTAL2
11
RESET
24
VCC
GND
N.C.
26
13
9, 17
48-TQFP
PIN #
4
22
23
35
20
16
21
9
TYPE
DESCRIPTION
I UART channel B Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles at
logic 0 but can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
O UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto
RS485 half-duplex direction control, see FCTR[3] and EMSR[3].
I UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
O UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
I UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
I UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
I UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
O Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to
the three state mode and OP2B# output HIGH when MCR[3] is set to a
logic 0. See MCR[3]. If INTB is used, this output should not be used as
a general output else it will disturb the INTB output functionality.
13
14
36
42
17
12, 24, 25,
37
I Crystal or external clock input. Caution: this input is not 5V tolerant.
O Crystal or buffered clock output.
I Reset (active high) - A longer than 40 ns HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held HIGH, the receiver input will be ignored and outputs are
reset during reset period (see Table 16).
Pwr 2.25V to 3.6V power supply. All input pins, except XTAL1, are 5V toler-
ant.
Pwr Power supply common, ground.
No Connection.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
REV. P1.0.0
PRELIMINARY
XR16V2750
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FIGURE 5. BAUD RATE GENERATOR
To Other
Channel
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL, DLM and DLD
Registers
MCR Bit-7=0
(default)
Fractional Baud
Rate Generator
Logic
MCR Bit-7=1
16X or 8X
Sampling
Rate Clock
to Transmitter
and Receiver
TABLE 5: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
400
2400
4800
9600
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
DIVISOR FOR
16x Clock
(Decimal)
3750
625
312.5
156.25
150
78.125
60
52.0833
39.0625
30
26.0417
20
15
13.0208
9.7656
7.5
6.6667
6.5104
6
5
3.75
3.2552
3
2
1.6276
1.5
DIVISOR
OBTAINABLE IN
V2750
3750
625
312 8/16
156 4/16
150
78 2/16
60
52 1/16
39 1/16
30
26 1/16
20
15
13
9 12/16
7 8/16
6 11/16
6 8/16
6
5
3 12/16
3 4/16
3
2
1 10/16
1 8/16
DLM PROGRAM
VALUE (HEX)
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DLL PROGRAM
VALUE (HEX)
A6
71
38
9C
96
4E
3C
34
27
1E
1A
14
F
D
9
7
6
6
6
5
3
3
3
2
1
1
DLD PROGRAM
VALUE (HEX)
0
0
8
4
0
2
0
1
1
0
1
0
0
0
C
8
B
8
0
0
C
4
0
0
A
8
DATA ERROR
RATE (%)
0
0
0
0
0
0
0
0.04
0
0
0.08
0
0
0.16
0.16
0
0.31
0.16
0
0
0
0.16
0
0
0.16
0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XR16V2750.PDF ] | |
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