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PDF XR16L570 Data sheet ( Hoja de datos )

Número de pieza XR16L570
Descripción SMALLEST 1.62V TO 5.5V UART
Fabricantes Exar Corporation 
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XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
DECEMBER 2005
GENERAL DESCRIPTION
FEATURES
REV. 1.0.0
The XR16L570 (L570) is a 1.62 to 5.5 volt Universal
Asynchronous Receiver and Transmitter (UART) with 5 volt
tolerant inputs and a reduced pin count. It is software
compatible to industry standard 16C450, 16C550,
ST16C580, ST16C650A, XR16C850 and XR16L580
UARTs. It has 16 bytes of TX and RX FIFOs and is capable
of operating with a serial data rate of up to 4 Mbps at 5V, 3
Mbps at 3.3V,1 Mbps at 2.5V and 750 Kbps at 1.8V. The
internal registers are compatible to the 16C550 register set
plus enhanced registers for additional features to support
today’s high bandwidth data communication needs. The
enhanced features include automatic hardware and
software flow control to prevent data loss, selectable RX
and TX trigger levels for more efficient interrupt service,
wireless infrared (IrDA) encoder/decoder for wireless
applications and a unique Power-Save mode to increase
battery operating time. The device comes in 32-QFN and
24-QFN packages in industrial temperature range.
APPLICATIONS
Handheld Terminals and Tablets
Handheld Computers
Wireless Portable Point-of-Sale Terminals
Cellular Phones DataPort
GPS Devices
Personal Digital Assistants Modules
Battery Operated Instruments
Smallest Full Featured UART
1.62V to 5.5V Supply Voltage
5V Tolerant Inputs (except XTAL1/CLK)
’0 ns’ Address Hold Time (TAH and TADH)
Software Compatible to industry standard 16C450,
16C550, ST16C580, ST16C650A, XR16C850 and
XR16L580
16-byte Transmit FIFO
16-byte Receive FIFO with Errors Flags
Selectable RX and TX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Up to 4 Mbps data rate at 5.0V Operation
Up to 3 Mbps data rate at 3.3V Operation
Up to 1 Mbps data rate at 2.5V Operation
Up to 750 Kbps data rate at 1.8V Operation
Infrared (IrDA) Encoder/Decoder
Complete Modem Interface
Power-Save Mode to conserve battery power
Sleep Mode with Wake-up Interrupt
Very small packages: 24-QFN (4x4x0.9mm) and 32-QFN
(5x5x0.9mm)
Industrial Temperature Grade(-40 to +85oC)
FIGURE 1. BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR#
IOW#
CS#
INT
RESET
Data Bus
Interface
*5 V Tolerant Inputs
(Except for CLK)
UART
UART 16 Byte TX FIFO
Regs
TX & RX
IR
ENDEC
BRG 16 Byte RX FIFO
Clock Buffer
VCC
(1.62 to 5.5 V)
GND
TX
RX
RTS#
CTS#
DTR#
DSR#
CD#
RI#
XTAL1 (CLK)
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XR16L570 pdf
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REV. 1.0.0
XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
1.0 PRODUCT DESCRIPTION
The XR16L570 (L570) is an enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its
features set is compatible to the ST16C580 device and additionally offers Power-Save to isolate the data bus
interface during Sleep mode. The XR16L570 can operate from 1.62V to 5.5V with 5 volt tolerant inputs. The
configuration registers set is 16550 UART compatible for control, status and data transfer. Also, the L570 has
16-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, transmit and receive FIFO trigger levels, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4. The L570 is fabricated
using an advanced CMOS process.
Enhanced Features
The L570 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L570 is
designed to work with low supply voltage and high performance data communication systems, that require fast
data processing time. Increased performance is realized in the L570 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time. In addition, the L570 provides the
Power-Save mode that drastically reduces the power consumption when the device is not used. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Bus Interface
The L570 provides a host interface that supports a microprocessor (CPU) data bus interface. The interface
allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CS# inputs for data bus
operation. See pin description section for details on all the control signals.
Data Rate
The L570 is capable of operation up to 4 Mbps at 5V, 3 Mbps at 3.3V, 1 Mbps at 2.5V and 750 Kbps at 1.8V
with 16X internal sampling clock rate by using an external clock source on the XTAL1 (CLK) pin.
Internal Enhanced Register Sets
The L570 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, infrared encoder/decoder enable/disable,
modem interface controls and status, sleep mode and Power-Save mode (in the 24-QFN package) are all
standard features. Following a power on reset or an external reset, the registers defaults to the reset condition
and it is compatible with previous generation of UARTs, 16C450, 16C550, 16C580, 16L580, 16C650A and
16C850.
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XR16L570 arduino
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REV. 1.0.0
XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
Transmit Shift Register (TSR)
ML
SS
BB
TXNOFIFO1
2.10.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Data Byte
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1,2 and Xon1,2 Reg.)
Auto Software Flow Control
T ransm it
FIFO
THR Interrupt (ISR bit-1):
- When the TX FIFO falls below the
programmed Trigger Level, and
- When the TX FIFO becomes empty.
FIFO is Enabled by FCR bit-0=1
16X Clock
Transmit Data Shift Register
(TSR)
T XF IF O 1
2.11 RECEIVER
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the falling edge of a
start or a false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start
bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is
validated as a start bit. Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Each of the data, parity and stop bits is sampled at the middle of the bit to prevent false framing. If
there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte
from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status
of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character
or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
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