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PDF XR16L2752 Data sheet ( Hoja de datos )
| Número de pieza | XR16L2752 | |
| Descripción | 2.25V TO 5.5V DUART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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xrwww.DataSheet4U.com
MAY 2005
GENERAL DESCRIPTION
The XR16L27521 (2752) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
operates from 2.25 to 5.5 Volt supply range and is
pin-to-pin compatible to Exar’s ST16C2552 and
XR16C2852. The 2752 register set is compatible to
the ST16C2552 and the XR16C2852 enhanced
features. It supports the Exar’s enhanced features of
64 bytes of TX and RX FIFOs, programmable FIFO
trigger level and FIFO level counters, automatic
hardware (RTS/CTS) and software flow control,
automatic RS-485 half duplex direction control output
and a complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Independent programmable
baud rate generators are provided in each channel to
select data rates up to 6.25 Mbps at 5 Volt and 8X
sampling. The 2752 is available in the 44-pin PLCC
package.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FIGURE 1. XR16L2752 BLOCK DIAGRAM
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
FEATURES
REV. 1.2.1
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s ST16C2552 and
XR16C2852
• Larger FIFO version of PC16C552
• Two independent UART channels
■ Reg set compatible to 16C2552 and 16C2852
■ Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt
and 3 Mbps at 2.5 Volt with 8X sampling rate
■ Transmit and Receive FIFOs of 64 bytes
■ Programmable TX and RX FIFO Trigger Levels
■ Transmit and Receive FIFO Level Counters
■ Automatic Hardware (RTS/CTS) Flow Control
■ Selectable Auto RTS Flow Control Hysteresis
■ Automatic Software (Xon/Xoff) Flow Control
■ Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode
■ Full modem interface
• Alternate Function Register
• Device Identification and Revision
• Crystal oscillator or external clock input
• Industrial and commercial temperature ranges
• 44-PLCC package
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
8-bit Data
Bus
Interface
*5 Volt Tolerant Inputs
(Except External Clock Input)
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Modem Control Logic
2.25 V to 5.5 V VCC
GND
TXA (or TXIRA)
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2752BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
REV. 1.2.1
Pin Description
NAME
CTSB#
44-PLCC
PIN #
28
DTRB#
DSRB#
CDB#
RIB#
MFB#
27
29
30
31
19
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
TYPE
DESCRIPTION
I UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
O UART channel B Data-Terminal-Ready (active low) or general purpose output. If this
pin is not used, leave it unconnected.
I UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
O Multi-Function Output Channel B. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set HIGH (see MCR bit-3). MCR bit-3 defaults to a logic 0 condition after a reset
or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
ANCILLARY SIGNALS
XTAL1
11
XTAL2
13
RESET
21
VCC
GND
44, 33
22, 12
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See Table 2 for more details.
I Crystal or external clock input. Caution: this input is not 5V tolerant.
O Crystal or buffered clock output.
I Reset (active high) - A longer than 40 ns HIGH pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held HIGH, the receiver
input will be ignored and outputs are reset during reset period (see External Reset
Conditions).
Pwr 2.25 to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.
Pwr Power supply common, ground.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
xr
REV. 1.2.1
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=1
OUTPUT Data Rate
MCR Bit-7=0
(DEFAULT)
DIVISOR FOR 16x DIVISOR FOR 16x
Clock (Decimal) Clock (HEX)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100 400 2304 900 09 00 0
600
2400
384 180 01 80 0
1200
4800 192 C0 00 C0 0
2400 9600 96 60 00 60 0
4800
19.2k
48
30 00 30 0
9600
38.4k
24
18 00 18 0
19.2k
76.8k
12
0C 00 0C 0
38.4k
153.6k
6
06 00 06 0
57.6k
230.4k
4
04 00 04 0
115.2k
460.8k
2
02 00 02 0
230.4k
921.6k
1
01 00 01 0
2.12 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and
TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
2.12.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.12.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
11
11 Page | ||
| Páginas | Total 49 Páginas | |
| PDF Descargar | [ Datasheet XR16L2752.PDF ] | |
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