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PDF XR16C2552 Data sheet ( Hoja de datos )
| Número de pieza | XR16C2552 | |
| Descripción | 2.97V TO 5.5V DUAL UART | |
| Fabricantes | Exar Corporation | |
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XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
DECEMBER 2004
GENERAL DESCRIPTION
FEATURES
REV. 1.0.0
The XR16C2552 (2552) is a dual universal
asynchronous receiver and transmitter (UART). The
XR16C2552 is an improved version of the PC16552
UART. The 2552 provides enhanced UART functions
with 16 byte FIFOs, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide the user with error indications and
operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Indepedendent
programmable baud rate generators are privded to
select transmit and receive clock rates from 50 Bps to
4 Mbps. The baud rate generator can be configured
for either crystal or external clock input. An internal
loop-back capability allows onboard diagnostics. The
2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to initialize both UARTs concurrently. The
2552 is available in the 44-PLCC package.
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
• 2.97 volt to 5.5 volt operation
• 5 volt tolerant inputs
• Pin-to-pin and functionally compatible to National
PC16552 and Exar’s XR16L2752 and XR16C2852
• 4 Mbps transmit/receive operation (64 MHz
External Clock Frequency)
• 2 Independent UART Channels
■ Register Set Compatible to 16C550
■ 16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
■ 16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
■ 4 selectable RX FIFO Trigger Levels
■ Fixed Transmit FIFO interrupt trigger level
■ Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
• DMA operation and DMA monitoring via TXRDY#
and RXRDY# pins
• UART internal register sections A & B may be
written to concurrently
• Multi-Function output allows more package
functions with few I/O pins
• Programmable character lengths (5, 6, 7, 8) with
even, odd, or no parity
• Crystal oscillator or external clock input
FIGURE 1. XR16C2552 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Modem Control Logic
3.3V or 5V VCC
GND
TXA (or TXIRA)
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2552BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
REV. 1.0.0
Pin Description
NAME
44-PLCC
PIN #
RIA#
43
TXB
RXB
26
25
RTSB#
23
CTSB#
28
DTRB#
27
DSRB#
29
CDB#
30
RIB#
31
ANCILLARY SIGNALS
XTAL1
11
XTAL2
13
RESET
21
VCC
GND
44, 33
22, 12
XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
TYPE
DESCRIPTION
I UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
O UART channel B Transmit Data. If it is not used, leave it unconnected.
I UART channel B Receive Data. Normal receive data input must idle at logic 1 condi-
tion. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
O UART channel B Request-to-Send (active low) or general purpose output. If it is not
used, leave it unconnected.
I UART channel B Clear-to-Send (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
O UART channel B Data-Terminal-Ready (active low) or general purpose output. If it is
not used, leave it unconnected.
I UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I Crystal or external clock input.
O Crystal or buffered clock output.
I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset period (see External
Reset Conditions).
Pwr 3.3V to 5V power supply. All inputs are 5V tolerant.
Pwr Power supply common, ground.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
xr
REV. 1.0.0
XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 or External clock frequency ) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x
MCR Bit-7=0
Clock (Decimal) Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00 0
2400
384 180
01
80 0
4800 192 C0 00 C0 0
9600
96
60
00
60 0
19.2k
48
30
00
30 0
38.4k
24
18
00
18 0
76.8k
12
0C
00
0C 0
153.6k
6
06 00
06 0
230.4k
4
04 00
04 0
460.8k
2
02 00
02 0
921.6k
1
01 00
01 0
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.10.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet XR16C2552.PDF ] | |
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