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PDF ICS813001I Data sheet ( Hoja de datos )
| Número de pieza | ICS813001I | |
| Descripción | LVPECL FEMTOCLOCK-TM PLL | |
| Fabricantes | ICS | |
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Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS813001I is a dual VCXO + FemtoClock™
Multiplier designed for use in Discrete PLL
loops. Two selectable external VCXO crystals
allow the device to be used in multi-rate appli-
cations, where a given line card can be
• One 3.3V or 2.5V LVPECL output pair
• Two selectable crystal oscillator interfaces for the VCXO,
one differential clock or one LVCMOS/LVTTL clock inputs
• CLK1/nCLK1 supports the following input types:
switched, for example, between 1Gb Ethernet (125MHz LVPECL, LVDS, LVHSTL, SSTL, HCSL
system reference clock) and 1Gb Fibre Channel
(106.25MHz system reference clock) modes. Of course,
a multitude of other applications are also possible such
• Crystal operating frequency range: 14MHz - 24MHz
• VCO range: 490MHz - 640MHz
as switching between 74.25MHz and 74.175824MHz
for HDTV, switching between SONET, FEC and non FEC
rates, etc.
The ICS813001I is a two stage device – a VCXO followed
by a FemtoClock PLL. The FemtoClock PLL can multiply
the crystal frequency of the VCXO to provide an output
frequency range of 40.83MHz to 640MHz, with a random
rms phase jitter of less than 1ps (12kHz – 20MHz). This
phase jitter performance meets the requirements of 1Gb/
10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel,
and SONET up to OC48. The FemtoClock PLL can also be
bypassed if frequency multiplication is not required. For
testing/debug purposes, de-assertion of the output enable
pin will place both Q and nQ in a high impedance state.
BLOCK DIAGRAM
• Output frequency range: 40.83MHz - 640MHz
• VCXO pull range: ±100ppm (typical)
• Supports the following applications (among others):
SONET, Ethernet, Fibre Channel, HDTV, MPEG
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.84 (typical)
• Supply voltage modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
VCO_SEL Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pullup
CLK0 Pulldown
CLK1 Pulldown
nCLK1 Pullup
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
VC
M2 Pullup
M1 Pulldown
M0 Pulldown
N2 Pulldown
N1 Pullup
N0 Pullup
OE Pullup
813001AGI
00
01
10
(default)
VCXO
11
0
VCO
PD 490-640MHz 1
Feedback Divider M
M2:M0
000 ÷16
001 ÷20
010 ÷22
011 ÷24
100 ÷25 (default)
101 ÷32
110 ÷40
111 MR
Output Divider N
N2:N0
000 ÷1
001 ÷2
010 ÷3
011 ÷4 (default)
100 ÷5
101 ÷6
110 ÷8
111 ÷12
www.icst.com/products/hiperclocks.html
1
Q
nQ
PIN ASSIGNMENT
VCO_SEL
N0
N1
N2
VCCO
Q
nQ
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24 CLK_SEL1
23 CLK_SEL0
22 OE
21 M2
20 M1
19 M0
18 CLK1
17 nCLK1
16 CLK0
15 VC
14 XTAL_IN0
13 XTAL_OUT0
ICS813001I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
REV. A SEPTEMBER 2, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ø)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
40.83
fVCO
tR / tF
odc
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N÷1
N ≠ ÷1
490
250
43
48
NOTE 1: Phase jitter using a crystal interface.
Typical
0.84
Maximum Units
640 MHz
ps
640 MHz
500 ps
57 %
52 %
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT
tjit(Ø)
fVCO
tR / tF
odc
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Phase jitter using a crystal interface.
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
20% to 80%
N÷1
N ≠ ÷1
40.83
490
250
43
48
0.87
Maximum Units
640 MHz
ps
640 MHz
500 ps
57 %
52 %
TABLE 5C.
AC
CHARACTERISTICS,
V=
CC
V=
CCA
V
CCO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ø)
fVCO
tR / tF
odc
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Phase jitter using a crystal interface.
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
20% to 80%
N÷1
N ≠ ÷1
40.83
490
250
43
48
Typical
1.2
Maximum Units
640 MHz
ps
640 MHz
500 ps
57 %
52 %
813001AGI
www.icst.com/products/hiperclocks.html
5
REV. A SEPTEMBER 2, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
R3
50
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3 R4
125 125
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
84 84
3.3V
LVDS_Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
100
3.3V
CLK
nCLK Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
LVPECL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
R3 R4
125 125
C1
C2
R5
100 - 200
R6
100 - 200
R1 R2
84 84
3.3V
CLK
nCLK HiPerClockS
Input
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
813001AGI
www.icst.com/products/hiperclocks.html
11
REV. A SEPTEMBER 2, 2005
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS813001I.PDF ] | |
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